I have a Verilog module acting as a register file (a slew of registers and some access ports) with a control signal coming from another module that controls when the write to one of the registers happens.
The idea is that I raise a control pin and the specified register is set to the value on one of the module's data inputs as follows:
module RegisterFile( input CLK, input [4:0] RegA_Name, input [4:0] RegB_Name, input [4:0] RegC_Name, input [31:0] RegA_In, input [31:0] RegC_In, input RegA_WrtEn, input RegC_WrtEn, output reg [31:0] RegA_Out, output reg [31:0] RegB_Out ); reg [31:0] r [31:0]; integer i; initial begin for(i = 0; i < 32; i = i + 1'b1) r[i] = 0; end always@(posedge CLK) begin RegA_Out <= r[RegA_Name]; RegB_Out <= r[RegB_Name]; if(RegA_WrtEn) begin r[RegA_Name] <= RegA_In; end if(RegC_WrtEn) begin r[RegC_Name] <= RegC_In; end end
I'm aiming for the register contents to get set and for that content to appear on the output on the same clock cycle that write enable gets set high.
I see the behavior that I'm shooting for when testing the module from a testbench, but when I wire it to the module that's actually going to be controlling it and test that, the write happens not on the clock cycle that write enable is set high, but two clock cycles after (depicted in the waveform below). Why might this be? How can I edit my code to achieve the behavior I'm shooting for, or something close to it?