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I am simulating a 2 stage miller opamp in LTSspice. I'm using the standard models provided by my uni. I can simulate the operating point, but in the operating point data, all capacitances are 0. I assume this is because LTSpice just sets all capacitances as open in the operating point analysis but I'm not sure. However, since I need to have an idea about these capacitances, I was wondering how I can get to them after doing the simulation. In the uni labs we use a tool (JMOSCal, designed by someone in our department a few years ago) that will give all these values, but it requires hSpice, which I don't have access to at home.

LTSpice clearly does calculate these values at some point, since my opamp doesn't have infinite bandwidth.

EDIT: I would like to mention the following: The reason I'm using LTSpice is because it's the best I have at home. I don't have access to the fancy Cadence or Mentor tools. LT spice is a good simulator in terms of accuracy. However, it's license does not permit the use of technology models from fabs. Predictive technology models do not fall under this clause, and hence can be used.

I would also like to point out that this is not a standard simple model, but a high acuraccy and advanced predictive technology model. We are talking about 200+ parameters per device type. They are available from this website: Arizona State PTM models page The one I am using is the "PTM High performance 45nm metal gate, High-K, strained-silicon".

I need to do high-accuracy simulations. The accuracy I can achieve with hand-calculations is not enough. Even if I could manually calculate them to any decent level of accuracy, I would not be able to just "add them" - LTSpice clearly does model them internally, because I can see poles and zeros that would not be there if no capacitance were modeled.

How do I find these values?

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  • \$\begingroup\$ Maybe your university model should incorporate capacitances? \$\endgroup\$ – Andy aka May 6 '17 at 11:16
  • \$\begingroup\$ The model does include them. This is a predictive technology model for 45nm - the same used in the JMOSCal tool - only difference is that JMOSCal uses hspice instead of ltspice. \$\endgroup\$ – Joren Vaes May 6 '17 at 11:24
  • \$\begingroup\$ 1) I do not believe LTspice is very suitable for simulation on-chip circuits. 2) Standard models aren't very suitable for simulating mosfets in 45 nm technology, many effects are not modelled. 3) A better approach would be for you to estimate which caps will determine the BW of your circuit (often there are only a few), determine their value by a hand calculation and insert them as an ideal capacitor in the circuit. Again, reliable models are essential as otherwise you're just guessing so any performance results will be unreliable. \$\endgroup\$ – Bimpelrekkie May 6 '17 at 14:15
  • \$\begingroup\$ I'm going to edit my original question to address some of these points. \$\endgroup\$ – Joren Vaes May 6 '17 at 14:20
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Those models are BSIM 4.0, and you will have to dig into the documentation to get the capacitance values and calculate them for your operating point. An example is here. You need to keep in mind that the capacitances are not fixed and will move with the voltages due to the depletion edges. This is why you cannot simply pull the capacitances from the file.

The greatest issue you will have is that these models do not represent anything that is real, so you have no way to have a high accuracy simulation, as per your desires. BSIM models are created by a bunch of gate sweeps and curve fits, which are create models that are good enough even through they are not true to the physics. On real nodes, we use surface based models, such as SPS or EKV (there are others) that follow the physics.

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  • \$\begingroup\$ Thanks for the reply! I realized I couldn't just pull them from a file. The sizing tool in our uni can give you a rough idea of the capacitances in a certain operating point, and I was hoping to get something similar out of LTSice - it would make it easier for me to get an idea of where my poles are, and what effect changing some value will have. I'll have to find some other way then! Thanks! \$\endgroup\$ – Joren Vaes May 10 '17 at 13:07
  • \$\begingroup\$ It's possible that you could just extract the DC operating point at a state in LTSpice. I do not know about LTSpice, but my internal simulator for EKV will give capacitance for each terminal on the device at a condition. LTSpice will calculate these, but if you can access them is another matter. \$\endgroup\$ – b degnan May 10 '17 at 13:34
  • \$\begingroup\$ It's the extraction of this information that I have difficulties with. It's hard to do design when you have no idea about the gm of your transistor in it's operating point in your circuit, or without knowing the capacitances, .... \$\endgroup\$ – Joren Vaes May 11 '17 at 13:04
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Though it has been more than one year since you ask this question, I think it might be helpful to leave a comment here in case someone has the same problem (like myself in twenty minutes ago). I find these values could be find in the log files named "yourschematicname.log" in the folder storing your schematics. This holds true for both BJT and CMOS. And I am sure that they vary when you modify the DC bias point.

Parasitic capacitances of BJT:

enter image description here

Parasitic capacitances of NMOS:

enter image description here

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