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For example, although they are not the same, I²C uses pull-up resistors and open drain drivers. Resistors, not the nodes, set the bus idle state. Many nodes can be added to the bus without loading the bus. Because all the drivers use open drain, many drivers can pull the bus low without any problems.

In CAN the nodes command the bus idle state. If many nodes are added to the bus how is loading avoided?

If all but one node command the bus to a dominant state, how does the one node that is still commanding the bus to a recessive state not get damaged?

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    \$\begingroup\$ Welcome to the site. Please quickly realise that this is not a free design house, homework-answering service or an on-line technical encyclopedia, copied out to you on demand. People will help you take the next step if your questions shows that you've done as much as you possibly could on your own - which your post doesn't, I'm afraid. Please revise your question showing your work and findings so far in detail. Or delete the question if Internet searches give you your answer anyway. This are very well documented principles of CAN. Again, a warm welcome to the site. \$\endgroup\$
    – TonyM
    May 6, 2017 at 12:28
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    \$\begingroup\$ It works in exactly the same way as I2C. It's just differential that's all. CANL is open drain to ground. CANH is open drain to VCC. \$\endgroup\$
    – Jon
    May 6, 2017 at 13:53
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    \$\begingroup\$ @TonyM Thank you for the welcome but i'm not new to the site. I'm not asking for design help because how the transceiver works internally is irrelevant to design. I am also not asking a home work question. I've been out of school for a year now. I'm just curious and all the documentation that i've found talks about how the bus works but not about the internals of the transceivers. \$\endgroup\$
    – vini_i
    May 6, 2017 at 14:00
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    \$\begingroup\$ @TonyM There is nothing on the site that warrants closing a question on the difficulty of the question. If its so easy to answer the question it might be better to answer it. Just my two cents. \$\endgroup\$
    – Voltage Spike
    May 8, 2017 at 6:40
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    \$\begingroup\$ @TonyM respectable move, thanks. \$\endgroup\$ Jan 22, 2020 at 10:48

1 Answer 1

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CAN has specifications for leakage currents and for capacitance of each node. More nodes will slow down the edge rate, but edge rates are controlled anyway, to establish a maximum interference. Fast edges will convolve with almost any system and inject energy; slow edges inject less energy thus interfere less, pleasing the FCC and easing EMI certification.

More nodes do load the bus, both with DC leakages and with capacitance. But the bus drivers are designed to handle the increasing capacitance. The receiver has a large minimum noise rejection (0.5 volt), thus across a 60 ohm termination a leakage of 0.5 V/ 60 Ω = 8 mA is tolerated cumulatively.

In recessive, the bus floats and the termination resistors discharge the bus to zero (or near-zero) differential voltage. The transistors connected to the CAN bus are required to survive, without damage, under massive overvoltage conditions such as 42 volts (MCP2551) though only a 12 volt battery be used.

This survive-without-damage is imposed on the transmitter and on the receiver CAN circuits. If all the nodes attempted to impose a dominant state, the maximum voltage imposed would be the battery voltage, which the receiver easily tolerates.

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    \$\begingroup\$ Re "If all the nodes attempted to impose a dominant state": This happens for the (first) ACK bit at the end of every CAN message (except the transmitter that doesn't impose a dominant state). And also for error frames. E.g. ref. MCP2515, page 7. \$\endgroup\$ May 27, 2017 at 12:59

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