# How to design a control bit to turn unsigned binary into two's complement?

I am designing a 4-bit comparator using only basic logic gates (and, or, nand, xor, etc.) In its current form, the comparator takes two 4-bit unsigned binary numbers (A and B) and compares each bit value from most to least significant and determines an output: A > B, A < B, or A = B. Pretty simple.

However, I am trying to add a control bit to signify whether the input is unsigned binary or two's complement. The default state, 0, should signify that the input is in unsigned binary, while 1 signifies that the input numbers are in two's complement.

I'm having difficult understanding how or where in the circuit to implement the control bit. I understand that one method is to implement an adder, but I'm not sure if it would have to exist outside of the circuitry I have already designed, and the control bit would switch between two circuits that exist almost independently of each other. I'm sure there has to be a more elegant, integrated solution. If you could just point me in the right direction, I would greatly appreciate it!

• don't write "and, or, nand, xor, etc". State explicitly what gates you mean – "basic" is a really relative word, and depending on what technology you design for, a 6bit lookup table might be the basic logic element. May 6, 2017 at 16:03
• This is obviously an assignment and you're not the first to post it, so you can just have a clue: see what your current circuit does when both numbers are positive and when both are negative, then consider how to deal with the other cases. May 6, 2017 at 16:05
• Is stack exchange not used for getting help with assignments? Genuinely curious, this is my first post here, and I don't know the rules/etiquette.
– Marg
May 6, 2017 at 21:59

You're correct in your intuition that there's a better solution than a multiplexor selecting between two entirely independent circuits.

Recall the meaning of a positional number system, for an unsigned input $a_3 a_2 a_1 a_0$ the value is $$8 a_3 + 4 a_2 + 2 a_1 + a_0$$

For two's complement, the only change is that the sign bit takes on a negative place value: $$-8 a_3 + 4 a_2 + 2 a_1 + a_0$$

Now, the condition for comparison of two signed two's complement numbers is

$$-8 a_3 + 4 a_2 + 2 a_1 + a_0 < -8 b_3 + 4 b_2 + 2 b_1 + b_0$$

Add the sign-bit terms to both sides, to get

$$8 b_3 + 4 a_2 + 2 a_1 + a_0 < 8 a_3 + 4 b_2 + 2 b_1 + b_0$$

which is the unsigned comparison between $b_3 a_2 a_1 a_0$ and $a_3 b_2 b_1 b_0$

That is, you can use your control input to swap the sign bit, then feed the normal comparison logic.

If a multiplexer isn't one of your fundamental gates, then this "swap" adds non-trivially to the complexity. So let's look at that inequality again:

$$-8 a_3 + 4 a_2 + 2 a_1 + a_0 < -8 b_3 + 4 b_2 + 2 b_1 + b_0$$

Add $8$ to both sides and group:

$$8 (1 - a_3) + 4 a_2 + 2 a_1 + a_0 < 8 (1 - b_3) + 4 b_2 + 2 b_1 + b_0$$

Note that $1-x$ is just the NOT operator.

$$8 \overline{a_3} + 4 a_2 + 2 a_1 + a_0 < 8 \overline{b_3} + 4 b_2 + 2 b_1 + b_0$$

and this is again the unsigned comparison logic applied to the two inputs $\overline{a_3} a_2 a_1 a_0$ and $\overline{b_3} b_2 b_1 b_0$

Now your control input only needs to select between $a_3$ and $\overline{a_3}$ (and likewise for $b_3$), and this is just the XOR function.

Finally, your dual-mode comparator is made by simply taking your working unsigned comparison circuit, and feeding its inputs with

$$(a_3 \oplus S) a_2 a_1 a_0$$ $$(b_3 \oplus S) b_2 b_1 b_0$$