Assuming you have it configured in the usual manner, this is what you are working with.

simulate this circuit – Schematic created using CircuitLab
Note a MOSFET is a capacitive input.
When turning it on. You need to charge C2. When it charges high enough the drain is going to drop to near zero, forcing the bottom end of C1 down to ~\$-48\$V, and the logic gate needs to drive more current to dump that charge.
Similarly, when you turn off the device, the logic gate needs to discharge C2 till the MOSFET turns off. That will drive the bottom end of C1 UP to \$48V\$. The logic gate then needs to pull current to allow C1 to charge.
Your logic gate gate has a maximum current it can push \$I_{OH}\$ or pull \$I_{OL}\$. You therefore need a series resistor to ensure that the current drawn does not exceed that value under the above conditions or else the resulting current or voltage at the pin will fry the gate.
As for a pull down. As long as the logic gate is not a driver than can go high impedance, this should not be necessary.
UPDATE AFTER YOU ADDED THE SCHEMATIC.
You can not use an n-channel MOSFET on the high side like that using simple logic drive. The controlling voltage is gate to source. With the load beneath the gate it will immediately turn itself off again as soon as current flows through the load. Then it will either oscillate probably frying the MOSFET. Further, you just added a much more complicated capacitor effects that will put a sustained load on the logic gate.