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I'm trying to connect two latches made by 74xx chips (normal output: 7404, 7408, 7432...), so that the inverted main output signal is latched into the first circuit on the falling edge and into the second circuit on the rising edge. Thus the main output will switch from low to high and vice versa every clock cycle.

The clock is a debounced push-button connected to a inverted to create sharp edges. The timing is done by sending the clock signal through more inverters.

Each circuit works perfectly when tested individually, but as soon as I connect the output of the first one to a input of the second one, it only latches correctly about 20% of the time.

To fix this problem I added a 1uF capacitor.

When testing the circuit, I found that on one AND-gate the output goes low before any input goes low. I tested it with a simple S-R-latch to check wich signal goes low first.

Here's the schematics:

schematic

simulate this circuit – Schematic created using CircuitLab

Here's the breadboard: enter image description here

The yellow wires at the bottom create a S-R-latch that I used for testing. The testing showed that the output of the first AND-gate on the third chip goes low first, then the clock signal (first input), then the output of the first OR-gate (second input).

What should happen (3rd chip, 1st gate): Clock goes low -> output goes low -> 2nd input on the 2nd AND-gate goes low AFTER the clock on the 2nd AND-gate goes high -> latch successful

What seems to happen: Output goes low (??) -> clock and 2nd input go low (on time) -> 2nd input on the 2nd AND-gate goes low BEFORE the clock on the 2nd AND-gate goes high -> latch unsuccessful

One might think that the output goes low too early, because the 2nd input goes low before the clock does. But that can't happen because the signal of the 2nd input depends on the same clock and goes through more transistors (is delayed). Yet holding the second input stable with a capacitor solves the problem.

So, how can the output of that gate go low before any of the inputs?

Why do both circuits work when separate (which means the 2nd input of their first AND-gates is manually pulled high or low) but not when the second latch gets its signal from the first one and vice versa?

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  • \$\begingroup\$ Circuit shows input clock only. What it is expected to latch? Where is (are) output? \$\endgroup\$ – Anonymous May 6 '17 at 21:28
  • \$\begingroup\$ @Anonymous The output is inverted and used as the input. The output changes from low to high and vice versa every clock cycle. \$\endgroup\$ – uzumaki May 6 '17 at 21:46
  • \$\begingroup\$ Where are your decoupling capacitors? \$\endgroup\$ – pericynthion May 27 '17 at 20:51
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WHen you ignore propagation delays with excessive delays from cascaded stages, then you see you had a Race Condition and forced the race with a big fat cap.

The proper design looks like below. note the number of stages from inputs to outputs is symmetrical.

enter image description here

Although the above is the topology for LS TTL and you are using HC CMOS, it doesn't matter for learning but the CMOS FF is made of Transmission Gates (TG)

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  • \$\begingroup\$ Almost the first thing that popped into my mind, reading the OP. (D-type edge-triggered so that as the clock exceeds its threshold, it locks out the inputs so that the ff isn't affected by more changes until another pulse.) Well, saved me time. +1 \$\endgroup\$ – jonk May 7 '17 at 3:43
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It turned out the clock signal was the culprit.

The transition of the clock signal was too slow, so the output of every gate that was directly or indirectly connected to the signal, changed its state in a slow manner. The propagation delay of the gates was not enough to compensate for this. Because the clock was halfway between HI and LO for a relatively long time, the latch was in a floating state and whichever gate stabilized first, defined the outcome.

The same problem also occured in the suggested Texas Instruments flip-flop design.

Using a SR-latch instead, allows for manual toggle between HI and LO that doesn't need debouncing and creates a clock signal with sharp edges. This clock signal has a low frequency, but sharp edges and does not cause the problems that occured before.

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