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I am designing a SMPS using FPS from Fairchild. But I am having a bit of doubt on how to get the output capacitance for my output. I am thinking that the method to obtain the capacitance will be the same for all SMPS designs. The only parameter I have is the ripple current Icap, but how to go about the other paramters is a bit of doubts.

I have attached a jpg off a cut of the explanation from this application note -
Application Note AN4137, "Design Guidelines for Off-line Flyback Converters Using Fairchild Power Switch (FPS)" 2003.
Maybe I get some help on this.

From Diagramenter image description here:

Parameters already derived are Icap(n), Io(n),Dmax,Fs,IdsPeak,Vro,Kl(n),Vo, and Vf.

Parameters i want to get is C(o),Rc(n).

Thanks.

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  • \$\begingroup\$ Firstly, whenever you talk about power supply design you should tell us what topology you're using. Secondly, whenever you include an excerpt from an application note, include a link to the note. See my edits above. \$\endgroup\$ – Adam Lawrence Apr 20 '12 at 13:08
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    \$\begingroup\$ There is a lot more to output capacitor selection than just ripple issues. The output capacitor effects the open loop response of the system, which can have a significant effect on the closed system depending on how it is controlled. \$\endgroup\$ – Olin Lathrop Apr 20 '12 at 13:11
  • \$\begingroup\$ @Madmanguruman Thanks for the AN4137. Expecting your help :) \$\endgroup\$ – Paul A. Apr 20 '12 at 13:18
  • \$\begingroup\$ @OlinLathrop Please more light to your response! \$\endgroup\$ – Paul A. Apr 20 '12 at 13:19
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In my experience, for most topologies the number of output capacitors required in a design is determined by the ripple current and not by the capacitance, because when you crunch the numbers, you'll find that the minimum capacitance you need to keep the output in regulation will be smaller than the ESR you need to keep the ripple voltage within reasonable limits (usually 1% of the DC output).

This is engineering, so it's always better to calculate rather than assume. Since you know the maximum load, the expected voltage on the capacitor and the on-time of the primary-side flyback switch (which is the period when no energy is transferred to the capacitor and it discharges to power the load) you can calculate how much the capacitor will discharge and determine what size of capacitor you need to keep reasonable regulation. Then, since you know the ripple current, you can calculate how many capacitors you need to keep the ripple voltage reasonable. Go with whichever calculation is larger.

Example

\$ \Delta V = \dfrac{I \times \Delta t}{C} \$

That is to say, a \$ 100 \mu F\$ capacitor being discharged by a 10A load over \$1 \mu s\$ will lose

\$ \Delta V = \dfrac{10A \times 1 \mu s }{100 \mu F} = 0.1V\$

Let's assume that the ESR of this capacitor is \$100 m \Omega\$ and the peak-to-peak ripple current is 4A (not unheard of for a flyback converter).

\$ \Delta V_{ripple} = \Delta I \times R_{ESR} \$

\$ \Delta V_{ripple} = 4A \times 100 m \Omega = 0.4V \$

SO: If 400mV ripple is too high, put more capacitors in parallel until the ESR is low enough to achieve the ripple you need.

As Olin commented, the stability of the converter is also a consideration when choosing output filter components, especially with flyback converters that operate in CCM. [If none of what I've taking about makes sense, you should seek counsel from someone experienced in power supply design.]

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  • \$\begingroup\$ Thanks once again. But I need to know how to go about the calculations you stated, especially in your second paragraph. Really, that is where I am stuck. (as to your last statement, that is the reason why I am here :) )Thanks. \$\endgroup\$ – Paul A. Apr 20 '12 at 13:36
  • \$\begingroup\$ +1 for the ripple current. I have encountered exactly what you describe, using more capacitors not because the extra capacitance was needed, but to not violate the ripple current spec of the capacitors. \$\endgroup\$ – Olin Lathrop Apr 20 '12 at 13:57
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There are two principal design elements for the output capacitor: capacitor ripple current and output voltage ripple.

1) Assuming operation at max load is deep into continuous conduction mode (CCM), output capacitor RMS current for a flyback (or a boost) is approximately Io*sqrt(D/(1-D)), where Io is the DC load current and D is the converter duty cycle (the fraction of time the power transistor is ON). (The power stage supplies current to the capacitor only when the power transistor is OFF, while the load draws current constantly. That's enough info to derive the formula, which assumes square wave currents (i.e. deep in CCM).) You can use the Dmax you calculated in the app note's "step -3".

2) That same pulsating ripple current creates voltage ripple via the capacitor esr Rc. (There's also ripple due to the capacitance charge and discharge (I/C*t), but that ripple is generally swamped by the esr ripple.) Peak-to-peak ripple is IoRc/(1-D) (with the same assumptions). Compare to your max ripple spec. (A second LC filter can be used to further reduce ripple.)

If you have to parallel capacitors, include some margin for unequal current sharing (20%?).

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It would be much easier to use one of the design tools. It is also advisable that before you start the prototype, to check the values manually. I am lazy so I will build with the Excel results, and use a plexiglass shield upon startup. as should always be done anyway.

SMPS/Fairchild Power Switch (FPS™) Excel-based Design Tools

The following tool does everything except wind the transformer and populate the board, but is for the lower power designs:

Power Supply WebDesigner

I am not an expert, but it is obvious that SMPSs are tightly controlled systems in themselves, and that one error in component value, or a poor or forgotten solder connection, will result in failure or burnout.

Further LC filtering, if necessary, is obviously critical, as the notes suggest.

It also looks like you are using 10 year old application material. You should go to the site and download the latest.

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