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I am going to implement a MAX10 remote update. Unfortunately, in Altera's documents i only see a NIOS implementation and everything looks very big and too complex. Also i already have a reliable communication channel, so i only need to store the data. I am still sure i can implement everything i need in VHDL, but i have some questions (and altera's documents are not very helpful):

  1. Is it enough to just address CFM, like user flash?
  2. What are relevant addresses? What is the image start?
  3. How do i start reconfiguration after flash is ready?
  4. Which file should i use for download?

Thanks!

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  • \$\begingroup\$ I fully agree with you that documentation is extremely unclear how to use it (however abounds a lot of technical details). I posted question to alteraforum yesterday (so far got only response that I must read documentation) and would be very interested in getting answer to your question here. \$\endgroup\$ – Anonymous May 7 '17 at 13:16
  • \$\begingroup\$ Seems like not many people want to answer :) \$\endgroup\$ – Gregory Kornblum May 7 '17 at 16:15
  • \$\begingroup\$ Right, I used to apply to Altera support for this type of issues. They are helpful. I will wait with my alteraforum question for several days, and will open support ticket with them. \$\endgroup\$ – Anonymous May 7 '17 at 17:39
  • \$\begingroup\$ I think i have got the answer. Will update once implemented... \$\endgroup\$ – Gregory Kornblum May 9 '17 at 11:09
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OK, i have just spoke to the local support.

So no problem in just using internal flash. The CFM should be enabled while creating the flash IP core- by default it is hidden. This is also the place to look up the base address to start writing the image.

The image is .rbf file generated by Quartus (probably out of .sof, i haven't tried it yet).

Last- to start running the image the FPGA has to do external reset. This is a little upsetting because i haven't prepared it in hardware, but i think i saw something in documents hinting that it's somehow also available from inside the FPGA. Will update if i find it.

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