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1)I need to design hardware for SPI communication with 2 different slaves. Slaves chip select pin is being pulled from high to low by the GPIO pin(port output)of the Master. But on the hardware design, I have only one port pin left. Can the same port pin be used to enable/disable the chip select pin of both the slaves? Response from both slave are obtained at different timing. Both slaves are not identical. Clock for both the slaves are derived from the system clock.The connection is as shown below (Fig1). Can this design possible for SPI communication?enter image description here Also can anyone tell which design (shown below) is recommended. Fig 2 or Fig3enter image description here Is it necessary that different slave should have its own SPI unit?
2) Which factor decide if daisy chain type SPI communication possible or not? Because in datasheet of both slaves it specifies, daisy chain type SPI communication is not supported. Does slave decides about the possibility of daisy chain type SPI communication?Can someone please explain how daisy chain communication happens?

Thanks

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  • \$\begingroup\$ Here are some unmentioned points that might help to clarify your question. Are Slave 1 and 2 identical? If different, do they share clock frequency and/or instructions length? The first question of part (2) is not clear, could you rephrase that? \$\endgroup\$ – FlyerDragon May 7 '17 at 16:04
  • \$\begingroup\$ Did you see en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus? \$\endgroup\$ – Anonymous May 7 '17 at 16:09
  • \$\begingroup\$ @FlyerDragon: I have modified my query. Both slaves are not identical. Clock for both slave is derived from system clock of master. \$\endgroup\$ – xyz101 May 7 '17 at 16:53
  • \$\begingroup\$ but the baud rate for both slave is different. \$\endgroup\$ – xyz101 May 7 '17 at 18:14
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The usual arrangement is to share MOSI and MISO between the slaves, and have a separate CS for each slave.

schematic

simulate this circuit – Schematic created using CircuitLab

This works if, like most SPI devices, your slaves are designed to not respond to inputs or drive their MISO outputs when CS is not asserted.

If Fig 1 is your current set-up, changing to this arrangement would actually free up GPIO lines.

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1) Put a not-gate built with a transistor (output taken from collector) driven from remaining port pin. Use output of this gate for one CS and use port output for the other one.

Note that you won't be able to de-select both chips. Which means, if you un-select one then the other will be selected.

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  • \$\begingroup\$ let's say if master pulls the CS pin from high to low, CS of both pins will be enabled, as per the fig1 shown. And since I am having 2 SPI units, I will use the TX and RX buffer of SPI to which slave is connected. For e.g if I want to communicate with Slave 1, I will use TX of MOSI1 and RX of MISO1. At that time TX of MOSI2 and RX of MISO2 will not be used, and viceversa. And clock is generated when microcontroller transmits data. So why I should i put a not gate? \$\endgroup\$ – xyz101 May 7 '17 at 17:03
  • \$\begingroup\$ You dont have to use seperate RX/TX pairs. Use one RX/TX for all chips and use different CS pins. That's how it should be done. Cheap and effective. Anyway, let me edit my answer to show the connection. \$\endgroup\$ – Rohat Kılıç May 7 '17 at 18:01
  • \$\begingroup\$ Are u telling about what i have shown in Fig 3? But what if both are communicating at different baud rate? Then i have to stop and initialise the baud rate every time.. So using common RX/TX will be beneficial for communicating with both the slave one at a time? \$\endgroup\$ – xyz101 May 7 '17 at 18:06
  • \$\begingroup\$ @xyz101 What you've shown in Fig-3 suggests common CS signal. If you provide different CS signals then yes, it will be the best. Also, baud rate is mostly not a concern for SPI. Why do you care about different baud rates? You should care about timing in terms of modes (e.g. Mode-3, Mode-0 etc depending on the clocking data of CLK's falling or rising edges). I abandoned editing my answer to show a connection diagram, btw. \$\endgroup\$ – Rohat Kılıç May 7 '17 at 18:16
  • \$\begingroup\$ ya actually modes are also different for both the slaves. But that doesn't answers my question. The master has two different SPI unit but want to use only one GPIO for driving the CS of both the slaves. Is that fine? \$\endgroup\$ – xyz101 May 7 '17 at 18:21
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You could use a single I/O pin to drive two chip selects, routing the I/O pin level directly to /CS1 and through an inverter to /CS2. It means that one device is always selected and it depends upon the SPI devices you have as to whether they'll like that. Some SPI devices communicate commands/data when /CS is asserted then action those commands/data when /CS is negated. You'll have to assess the devices you have yourself. Generally, avoid it if at all possible, it complicates your software.

The benefit of each SPI device on its own SPI master versus a shared SPI bus depends on the application.

You'd favour a shared SPI bus when you only have one master or when the PCB is very dense and you want to route fewer tracks.

You'd favour an SPI master per SPI device when the bus is going to a PCB connector, causing a long bus length that also could could be shorted off-PCB and kill the whole bus. Or when your SPI devices need fast transfers or transfers at precisely-timed intervals which stop you just alternating between devices.

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  • \$\begingroup\$ let's say if master pulls the CS pin from high to low, CS of both pins will be enabled, as per the fig1 shown. And since I am having 2 SPI units, I will use the TX and RX buffer of SPI to which slave is connected. For e.g if I want to communicate with Slave 1, I will use TX of MOSI1 and RX of MISO1. At that time TX of MOSI2 and RX of MISO2 will not be used, and viceversa. And clock is generated when microcontroller transmits data. So why I should i put a not gate? \$\endgroup\$ – xyz101 May 7 '17 at 17:05
  • \$\begingroup\$ Oh, suddenly 2 SPI masters is OK? Not what your original question said is it, that's why both of us suggested an inverter. Explain why 2 masters and not 1 master then? \$\endgroup\$ – TonyM May 7 '17 at 17:39
  • \$\begingroup\$ its like, One master has 2 SPI units. First Unit: MOSI1, MISO1, CS1, CLK1. Second Unit: MOSI2, MISO2, CS2, CLK2. This is what I have mentioned in Fig1. SO is it ok, to have one port pin for both the slave? \$\endgroup\$ – xyz101 May 7 '17 at 17:50

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