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What happens to an 8085 system if a square wave signal of 1KHz frequency is applied to the HOLD signal of 8085?

The frequency of operation is 2MHz. Therefore, if the every 0.5ms, the HOLD pin goes HIGH and then goes low. Within the 0.5ms, The processor has 1000 T states, so the microprocessor would simply be held tri-stated for that long after it sends the HLDA signal and after 0.5ms automatically we'd resume normal operation? I'm unsure about my answer so please help me out.

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  • \$\begingroup\$ To add to @TonyM's comment, at some point later the processor would assert HLDA and then relinquish the bus. On the other side, it would grab the bus back about a half-cycle after the HOLD goes inactive. \$\endgroup\$ – jonk May 7 '17 at 18:57
  • \$\begingroup\$ Be certain that master clock continues with 2 MHz while processor is holding...there is a maximum spec on clock period of 2 uS. And be aware that after HLDA goes hi, the CPU bus isn't fully tri-stated for a short period (about half a T-state). \$\endgroup\$ – glen_geek May 7 '17 at 19:12
  • \$\begingroup\$ @glen_geek, the minimum clock in a dynamic logic CPU is a general thing isn't it, it's not particular to bus mastership. \$\endgroup\$ – TonyM May 7 '17 at 19:30
  • \$\begingroup\$ @TonyM Perhaps I'm pedantic, but that master clock is the one thing that must continue (along with DC Vcc), else the processor's internals drift into unknown states sometime during "hold". A static-logic CPU could get along with only Vcc. \$\endgroup\$ – glen_geek May 7 '17 at 20:03
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    \$\begingroup\$ @TonyM yes, yes we agree. Since OP mentioned 2MHz clk, so did I. Clk is not specifically related to hold condition. Your answer is very fine not mentioning clk - we all just assume that CPU is clking all the time, because that's what dynamic CPU's require. \$\endgroup\$ – glen_geek May 7 '17 at 20:46
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Yes, what you describe is pretty much it.

The CPU would complete the current instruction before responding to the bus request. So the bus grant period may well be several clocks less than 1000 T states while that instruction's finished off first.

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