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Here is my code for an n mod k counter in VHDL. I keep getting various syntax errors but can't seem to pin down exactly what I'm doing wrong. Any help would be appreciated.

   library ieee;
   use ieee.std_logic_1164.all;
   use ieee.std_logic_arith.all;
  use ieee.std_logic_signed.all;

 entity nmodkcounter is generic (
n : natural := 4;
k : natural := 10);

port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
load    : in STD_LOGIC;
settime : in STD_LOGIC_VECTOR;
Q1 :  out STD_LOGIC_VECTOR(n-1 downto 0);
Q2 : out STD_LOGIC_VECTOR(n-1 downto 0));


signal value : std_logic_vector(n-1 downto 0);
begin
PROCESS(clock, reset_n, load, k)
begin
if ((reset_n = ’0’) and (load = '0')) then --Resets LINE 22
value <= (OTHERS => ’0’); -- LINE 23
elsif (clock’event and clock = ’1’) --Counts up at rising edge LINE 24
then value <= (value + 1);
elsif (reset_n = '0' and load = '1') then --Sets time to loaded value
value <= settime;
end if;

if(value = k - 1)  -- Resets count when value reaches k
then
Q1 <= '1'; -- Loads Q1 with 1 to send to next counter
value <= '0';
else
Q1 <= '0';
end if;
end process;

Q2 <= value; -- To output to display
 end nmodkcounter;

Errors

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  • \$\begingroup\$ From my experience, VHDL is annoying as hell when it comes to errors. Regardless, those n and k declarations may be the source of your errors. Can't tell though; you should post the errors you are getting in the question which would be more helpful \$\endgroup\$ – bit0fun May 7 '17 at 21:13
  • \$\begingroup\$ Hi sorry I will in a sec \$\endgroup\$ – Will May 7 '17 at 21:14
  • \$\begingroup\$ they are all syntax near text '...' expected '...' if that helps for now but will post screenshot in moment \$\endgroup\$ – Will May 7 '17 at 21:15
  • \$\begingroup\$ You need to post the errors and post your source with line numbers otherwise you can't correlate the two. \$\endgroup\$ – TonyM May 7 '17 at 21:16
  • \$\begingroup\$ Also, you're doing all sorts of stuff outside the clocked part in a clocked process. That's just asking for trouble. Assigning single bits to 4-bit vectors won't help either. \$\endgroup\$ – Brian Drummond May 7 '17 at 21:19
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You have the errors because you have wrong structure of the code. You need to close entity declaration and start architecture description:

...
Q2 : out STD_LOGIC_VECTOR(n-1 downto 0));
end nmodkcounter;

ARCHITECTURE behavior OF nmodkcounter IS 

    signal value : std_logic_vector(n-1 downto 0);
...

Next error is using parameter from generic in sensitivity list PROCESS(clock, reset_n, load, k). You need to remove from sensitivity list the k parameter.

Next error in follow assignments:

if(value = k - 1)  -- Resets count when value reaches k
then
    Q1 <= '1'; -- Loads Q1 with 1 to send to next counter
    value <= '0';
else
    Q1 <= '0';
end if;

Here the signals Q1 and value are std_logic_vector but you try to assign just one bit.

And as you forgot to start architecture description you need to close it in the end as end behavior; So your code should have the following structure:

entity nmodkcounter is 
    generic (
    ...
    );
    port (
    ...
    );
end nmodkcounter;

ARCHITECTURE behavior OF nmodkcounter IS 
...
begin
...
end behavior;
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