I am making a 64x32 bit SRAM, I need to use a 6x64 decoder as the Row address decoder. My question, is it possible to design a 6x64 Decoder using 3x8 Decoders?
Feed the same three lower address bits to eight 3x8 decoders, whose outputs (8x8 = 64 bits) are your row select lines. Use the upper three address bits as the inputs for a single 3x8 decoder, whose outputs select one of the 8 decoders at a time by controlling the enable input.
An alternative is to use one 3x8 decoder for the upper three address bits, another for the lower three bits. You'd then take one of the eight outputs from each of the two decoders, and AND them together. There would be 64 such combinations, so you'd have 64 AND gates, each mapping to an unique address.
Yes, very much. You can cascade decoders to produce any depth of decoding you want, providing you can tolerate the overall propagation delay.
You don't say if you're using discrete logic ICs such as 74LVC138 or using 3-to-8 decoder macros/etc in something like a CPLD/FPGA or in theory.
As well the 3-bit encoded bus, a 74LVC138 contains three enable inputs: two active low, one active high. You can put a first 74LVC138 on encoded bus bits E[5:3] and that will give you eight enables that each enables one of eight second-level decoders hanging off of E[2:0]. That uses nine 74LVC138s.
A true 3-to-8 decoder may not have an enable input. You can then sacrifice one of its three inputs to make an enable and use it as a 2-to-4 decoder. If its input bit 2 of 2:0 is used as a decoder 'high to enable', the lower 4 of the decoder's 8 outputs cannot be used because they will be active when this bit2/'enable' is low and that's being used as disabled. Use the decoder's higher 4 outputs. Now it's just using these 2-to-4 decoders to make to a tree where a decoder on E[5:4] produces enables for decoders on E[3:2] which produce enables for decoders on E[1:0], similar to the 74LVC138 example above.