I am designing a power-constrained device that has to gather some data, run from a battery for a couple of years and send data periodically. I want to ensure high reliability, because the device will not be easily accessible.

The MCU is an EFM32. Most of the time all sensing is handled by hardware peripherals. RAM is retained. RTC is running and periodically waking the CPU (let's say once every 24h).

I can turn the watchdog on when the CPU is woken up. Maximum watchdog period is around 250 seconds, which is much shorter than my sleep time. I know that it may save the day if the application hangs while CPU is active, but are there any design patterns that improve reliability when the CPU is sleeping? I don't have power budget for another chip or a second MCU.

  • \$\begingroup\$ Can you do anything when the only thing you have powered is the RTC, and the interrupts to awaken on RTC? Not really. If you did have the budget for a second MCU, then they could each check whether the other had woken up recently, but what would you do with that data? You could build a CMOS (very low power) side circuit that monitors power and latches on power out, and stores a number to be compared against RAM, does that count as a 'chip', does that do anything useful? To check something, you need two sources to check, and you've only got one, and say you can't afford a second. Won't work. \$\endgroup\$ – Neil_UK May 8 '17 at 6:04
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    \$\begingroup\$ You can build R+C oscillators running on 50nanoAmps. Given 2 volt swings, and 20nA charging 2uF, with dV/dT = I/C = 0.01 volt per second, that 2 volt delta requires 200 seconds. Clock that into CMOS ripple counter. \$\endgroup\$ – analogsystemsrf May 8 '17 at 6:11
  • \$\begingroup\$ @analogsystemsrf ... like the 4020, 4040 or 4060 for instance \$\endgroup\$ – Neil_UK May 8 '17 at 7:02

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