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I need to create a circuit based around one of Analog Digital DDSs (AD9102) to create a sinusoidal signal at 150kHz. For this purpose I think that a clock line at around 10MHz would be sufficient. I don't fully understand how the input clock works. By looking at the component's datasheet (@pag 20/36, CLOCK INPUT) I can see there are multiple possibilities for driving the chip. There are few things I don't fully comprehend.

  1. When they say "In applications where the analog output signals are at low frequencies, the AD9102 clock input can be driven with a single-ended CMOS signal". What do they mean by "low frequency"? Is 150kHz considered a low frequency output signal, or they mean something more like 100Hz signals?

  2. If solution 1 is not suitable for my case, I'd need to use a differential signal for the clock distribution. Let's suppose I will use the solution that includes the LVDS driver, what do they mean by CLK+ and CLK- (input signals of the AD9515 driver)? Assuming CLK+ is a 50% duty cycle squarewave @10MHz, does that mean CLK- is a 90° shifted version of CLK+ signal? If this is the case, why can't I simply put these signals into the CLKP and CLKN inputs, in order to avoid the use of the driver?

Hopefully everything makes sense! Thanks for the responses.

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  • \$\begingroup\$ Can you accept just 2 samples (0v, +1v) in each output cycle? Do you want 5 or 10 or 100 samples, to construct a low distortion? The IC has 4096 word internal storeage; do you plan to use all of those? If you use 10MHz clock (connected to +Clk, with the -Clk bypassed as shown), to produce 150KHz, you'll have 60 samples per cycle, or 15 samples (every 6 degrees) in one quarter cycle. How clean must your 150KHz be? 100dB SNR? \$\endgroup\$ – analogsystemsrf May 8 '17 at 16:15
  • \$\begingroup\$ How did you compute the 10MHz to 0.15MHz is sufficient ratio? Will samples every 6 degrees (0.1 radian error, at zero crossings) provide adequate reconstruction of the sinewave? How will you know what is "clean enough"? \$\endgroup\$ – analogsystemsrf May 8 '17 at 16:23
  • \$\begingroup\$ This project comes out of some specifications I've been given. Sadly I've never been told anything about the signal "cleanliness", which is the reason I decided to reconstruct the sinewave using at least 50 points per period (which by using the 10MHz clock is greatly respected). Do you think I should increase the clock in order to have more points (let's say at least 200-300 point per period)? Thank you very much for your reply! \$\endgroup\$ – NotSure May 8 '17 at 17:20
  • \$\begingroup\$ Go ask about the signal cleanliness requirements. Better to ask early on. \$\endgroup\$ – analogsystemsrf May 9 '17 at 5:10
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1) They mean the clock input is low frequency. A 10MHz clock is 'low frequency' in the context of this part, and single ended CMOS should be fine.

2) CLKP and CLKN are 180 degrees out of phase, intended to comprise a differential signal. Generally we like differential signals for clocks because they a) isolate common mode signals and b) have twice the slew rate as a single ended.

Whether you use a clock driver or not is up to you. The parts they suggest, AD9510 and the like, are clock distribution buffers. If you already have a clean LVDS 10MHz signal, then there's no need to use an additional buffer. If you have a single ended CMOS signal, use that. Use the appropriate coupling for either.

Note the absolute max and min voltages for the clock inputs, they should not go outside the digital supply rail and ground. Choose a rail voltage for your CMOS clock output no higher than that used for the 9102.

A 10MHz clock with a 150kHz output gives you plenty of leeway to design your output anti-alias (aka reconstruction) filter.

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  • \$\begingroup\$ Thanks for your reply! I think I will go for the single-ended solution since I find it easier. I find hard to come up with a solution to create two squarewave signals in phase opposition (probably because I've not studied enough circuits yet). The first thing that comes to my mind to create the CLK- once the CLK+ is given, is to use a NOT gate but I'm pretty sure that the propagation delay would mess everything up! \$\endgroup\$ – NotSure May 8 '17 at 17:26
  • \$\begingroup\$ When generating clk+ and clk-, one route is to use a differential driver, in which the delays are accurately matched, there are plenty to choose from. Another is to use a dedicated clock distribution chip, like the ad9510. Another (illustrated in the 'clock driving' section) is to use a transformer. If you have an LVDS signal, then you already have a well matched differential pair. \$\endgroup\$ – Neil_UK May 8 '17 at 18:59
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Try this on the DAC output

schematic

simulate this circuit – Schematic created using CircuitLab

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