I need to create a circuit based around one of Analog Digital DDSs (AD9102) to create a sinusoidal signal at 150kHz. For this purpose I think that a clock line at around 10MHz would be sufficient. I don't fully understand how the input clock works. By looking at the component's datasheet (@pag 20/36, CLOCK INPUT) I can see there are multiple possibilities for driving the chip. There are few things I don't fully comprehend.
When they say "In applications where the analog output signals are at low frequencies, the AD9102 clock input can be driven with a single-ended CMOS signal". What do they mean by "low frequency"? Is 150kHz considered a low frequency output signal, or they mean something more like 100Hz signals?
If solution 1 is not suitable for my case, I'd need to use a differential signal for the clock distribution. Let's suppose I will use the solution that includes the LVDS driver, what do they mean by CLK+ and CLK- (input signals of the AD9515 driver)? Assuming CLK+ is a 50% duty cycle squarewave @10MHz, does that mean CLK- is a 90° shifted version of CLK+ signal? If this is the case, why can't I simply put these signals into the CLKP and CLKN inputs, in order to avoid the use of the driver?
Hopefully everything makes sense! Thanks for the responses.