# Enable output for 1 clock-cycle?

Given input X and output Y and a clock - X is a button/switch and Y is equal to 1 only once per clock-cycle and button press.

The button is asynchronous and Y should only switch to 1 at clock rise.

I tried making a a time-diagram, not sure if it helps.

I tried to use D-flip flops but I have not come to any solution.

## 3 Answers

If input pulses are guaranteed to have high and low times that are at least a clock cycle long, but may arrive arbitrarily close to a clock edge, pass the input through three consecutive flip-flops, and AND together the non-inverted output of the second with the inverted output of the third. Note that the output would be delayed by a full clock cycle, but one could be reasonably assured of getting a one-clock-wide pulse even if the pulse arrives near a clock edge in violation of setup/hold requirements. If the first flop were omitted, the output would arrive a cycle sooner, but glitches might appear on it if an incoming pulse violates setup/hold requirements.

simulate this circuit – Schematic created using CircuitLab

An alternative approach if high pulses may be arbitrarily short, but will be separated by at least three clock cycles, would be to have a chain of three flops fed not by the pulse input, but by a flop which clocks the inverted output of the third flop's state.

simulate this circuit

Note that in this second version, it's necessary to use an XOR rather than an AND-NOT circuit, since an incoming pulse will effectively toggle the state of the signal being propagated through the flops. Note also that the second version may malfunction if a pulse is received near the third clock edge following an earlier pulse, due to a setup/hold violation on the first flop.

What you're looking for is called a one-shot circuit. Here's an implementation using D flip-flops with asynchronous resets:

According to Anonymous, that has issues with metastability. Alternately, you could try this more complicated circuit:

simulate this circuit – Schematic created using CircuitLab

Note that different implementations will have slightly different behavior. Bradman175 already pointed out one such difference. In a complete system, you would also need to consider things like switch debouncing and the suppression of start-up glitches.

• Ahh you beat it to me. Anyways my solution requires a mess of logic gates. May 8, 2017 at 22:39
• In practice this circuit is prone metastability. Ideally GPIO input must be synchronized with bus clock to ensure there're no timing violations for trigger devices. May 8, 2017 at 22:40
• Btw both of our circuits are susceptible to power-down glitches. May 8, 2017 at 23:01
• The second circuit is also prone to metastability and other problems. If the input changes at about the same time as clock, it would be possible for the lower-left register to catch the input on the clock cycle before the upper-left register, thus yielding either a runt output or no output at all. Or the upper-left register could catch the signal first, yielding an output which goes high for two full clocks. May 8, 2017 at 23:06
• You're killing me here, guys. That's what I get for making up digital circuits on the fly after 5pm. :-) May 8, 2017 at 23:12

Although my answer pretty much does the same as Adam Haun's just with more components, my circuit differs slightly. In that one shot circuit, if you quickly pulse (turn on then off quickly) between the clock's rise times, next time the clock rises, it will still activate the output. In my circuit, it does not activate the output if you do that. Not sure which is better.