First, download 8086 datasheet for reference.
When the 1MB of memory is referred to, do the books refer to the ROM and RAM of the computer.
They refer to the addressable space of the microprocessor. Look into datasheet, it shows A19:A16 and AD15:AD0 lines which are used for addressing outer space during T1 cycle. CPU does not care what is there in the outer space, it just tells there that it wants contents of the specific address.
Is the ROM + RAM = 1MB of memory interfaced?
You can have ROM, RAM and anything responding on the data bus to the CPU when it requests specific address. ROM and RAM are just most common types of devices which will respond.
when memory mapped I/O is shown as a memory segment in this 1MB memory space
Look here. CPU uses one pin to identify to its outer world type of command it uses for access (read [RD] or write [WR]), its name is M/IO. If this pin is high, command CPU executing is MOV instruction, and contents are expected from memory space. When this pin is low, CPU is executing IN/OUT instruction, and contents are expected from input/output device.
However, nothing prohibits the would-be I/O device to respond when this M/IO pin is high, and be like a memory.
In general, these types - memory space and I/O space were designed in the old good days when RAM was scarce and logic was expensive; having separate I/O circuitry will free up memory addressable space, and was smaller than memory addressable space (e.g. 16 bit, or even 8 bit instead of 20/16 bit). It was convenient and understandable.
However some designers of the devices decided that they would want their would-be I/O devices to respond to RAM cell reads and writes, rather than to port read/writes - the reasons could be that RAM I/O is faster, takes up less instruction bytes etc.
do they mean that the I/O ports is taking some of the RAM memory?
Yes - memory mapped I/O device, responding to the read/write request in memory addressable space, takes that space out of RAM useful space. For example, in older 8-bit computers with slotted RAM designers often implemented floppy disk controller I/O (which is input/output rather than memory device) registers to be addressable through special RAM locations.