I'm trying to figure out how to correctly connect 200MHz LVDS oscillator (DSC1103CE1-200.0000T Datasheet) to ICE40LP1K-QN84 FPGA. After reading Lattice's guide to differential signals (Link) this is the routing I've come up with.Current routing CLK_N and CLK_P are connected to IOL_6A and IOL_6B_GBIN7 respectively as recommended in the guide. They are also connected through 100 Ohm resistor (R6). Due to the manufacturing limitations I'm unable to breakout double row QFN-84 package on the single layer, that is why I've routed the signals on the bottom layer.

I would like to know if my routing is acceptable or not. Should I also length-match these two clock inputs? Right now they are 5.39mm and 4.65mm.

Thanks for any advice, it's much appreciated.

  • \$\begingroup\$ I'd try to length match. Possibly loop in towards the via's from the top left diagonal and split out (so that it is symmetrical) \$\endgroup\$ May 9, 2017 at 21:04
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    \$\begingroup\$ Although to be fair for 6mm of trace you are looking at <lambda/16 for a 200MHz clock (up to 7th harmonic) - transmission line affects are pretty negligible, so I imagine it will work absolutely fine. \$\endgroup\$ May 9, 2017 at 21:07
  • \$\begingroup\$ @TomCarpenter, that is the recommended layout (latticesemi.com/~/media/LatticeSemi/Documents/ApplicationNotes/…). The only other place I could move these two vias is the center of landing pad, which I would rather not do. Besides, it would make little difference. I can try looping it from the left diagonal, thank you! \$\endgroup\$
    – Lee Brown
    May 9, 2017 at 21:15
  • \$\begingroup\$ That's fine, couldn't tell if there would be space. I agree about not sticking the vias in the centre of the pad. \$\endgroup\$ May 9, 2017 at 21:21
  • \$\begingroup\$ What is track width to gap to gnd plane ratio, thus Zo? If. no gnd plane then interleaved gnd with a design for differential impedance coplanar tracks. Multiple micro bias can reduce inductance, but generally poor for Zo \$\endgroup\$ May 9, 2017 at 22:00

1 Answer 1


Signal Critical Length

How long a PCB Trace can be before we MUST pay attention to Impedance Control.

Function of Frequency (1/16th Wavelength)

\$ l_{critical} = \frac {c}{f} * \frac{1}{ 16* \sqrt{ε_{eff}}} \$


  • At 1 GHz = approx .425” = 10.8mm (Microstrip- FR4)

  • At 1 GHz = approx .375” = 9.5 mm (Stripline - FR4)

- since rise time BW (-3dB)= 3 /Tr for 10~90%

  • and your 200MHz clock has rise time 0.2ns , BW = 15GHz

However your impedance is not controlled so one can only guess how many cycles of ringing will occur if the tracks were several hundred ohms reactance The Q can be determined and then amount of overshoot/undershoot.

If the undershoot crosses gate threshold then that gate will experience jitter of about 10~20% on the edge of that gate. If undershoot ringing did not reach Vss/2 then no possible edge jitter would occur.

Your design needs more care in Zo design as it is marginally ok, but I would need a 3D model of the clock path with more details.

So all I can say is it is marginal.


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