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I started a digital design - a high precision time counter actually - that will be implemented on a Xilinx FPGA. I will describe it in VHDL.

I read several papers about this subject and I found about that I can use multiphase clocking {0°, 90°, 180°, 270°} in order to reach a higher sampling frequency. I can use the Xilinx IP PLL (clocking generation) for doing the heavy lifting.

The thing that's been puzzling me with multiphase clocks is : why using a four-phase clock in quadrature {0°, 90°, 180°, 270°} when you can just trigger your process on the falling edges of a two-phase clock in quadrature {0°, 90°}?

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  • \$\begingroup\$ Because most FPGAs don't really have falling edge clocked registers, just rising edge \$\endgroup\$ – Claudio Avi Chami May 11 '17 at 1:43
  • \$\begingroup\$ Sure looks obvious when I look at it that way. How can I know that the flip-flop can be triggered by a negative edge? I have an Artix-7 XC7A100T-2CSG324C. \$\endgroup\$ – VHDL May 11 '17 at 9:07
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I could envision a finite state machine (digital circuit) which had multiple clock edges available to trigger on so that some device could perform it's task 1/4 or 1/2 clock earlier, and maybe squeeze an extra step into the same amount of time. But as the designer if you don't see a benefit for it in your application then you would probably be better off basing the design on a simple clocking system and not trying to get too fancy.

Certain devices, like microprocessors, benefit a lot by utilizing multi-phase clocks. But I have designed a lot of state machines and I have always been able to do what I needed to do with a single fast clock.

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  • \$\begingroup\$ I totally get your point, but the thing here is that a time-to-digital converter is designed to measure very short periods e.g. less than 1ns. Articles online recommends FPGA or ASIC (for the hardware counter) clocked by a four-phase clock. \$\endgroup\$ – VHDL May 11 '17 at 9:21
  • \$\begingroup\$ That changes things a lot. Intervals of under a nsec are a different animal. I'll be interested to read what you discover. \$\endgroup\$ – Entrepreneur May 11 '17 at 12:23

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