I started a digital design - a high precision time counter actually - that will be implemented on a Xilinx FPGA. I will describe it in VHDL.

I read several papers about this subject and I found about that I can use multiphase clocking {0°, 90°, 180°, 270°} in order to reach a higher sampling frequency. I can use the Xilinx IP PLL (clocking generation) for doing the heavy lifting.

The thing that's been puzzling me with multiphase clocks is : why using a four-phase clock in quadrature {0°, 90°, 180°, 270°} when you can just trigger your process on the falling edges of a two-phase clock in quadrature {0°, 90°}?

• Because most FPGAs don't really have falling edge clocked registers, just rising edge May 11, 2017 at 1:43
• Sure looks obvious when I look at it that way. How can I know that the flip-flop can be triggered by a negative edge? I have an Artix-7 XC7A100T-2CSG324C.
– VHDL
May 11, 2017 at 9:07

"The thing that's been puzzling me with multiphase clocks is : why using a four-phase clock in quadrature {0°, 90°, 180°, 270°} when you can just trigger your process on the falling edges of a two-phase clock in quadrature {0°, 90°}?"

One reason is that in sampling applications, the edges used for sampling need to be precisely, and evenly spaced (in time) from one another. For example, if you want to sample something at 400 MHz using 4 phases of a 100 MHz clock, you want those rising edges (assuming that's what's being used for sampling) to be at T0, T0+2.5000ns, T0+5.0000ns, and T0+7.5000ns (may have left off some zeros here). If that is not the case, then you introduce phase noise into the sampled quantity which affects post processing and analysis.

If you try to do that using both edges of a 200 MHz (in this example) clock, the duty cycle of the clock needs to be precisely controlled to be 50.000%. This is much more difficult to do than generating 4 phases of a 100 MHz clock offset by 90 deg (2.5 ns) from each other.

I could envision a finite state machine (digital circuit) which had multiple clock edges available to trigger on so that some device could perform it's task 1/4 or 1/2 clock earlier, and maybe squeeze an extra step into the same amount of time. But as the designer if you don't see a benefit for it in your application then you would probably be better off basing the design on a simple clocking system and not trying to get too fancy.

Certain devices, like microprocessors, benefit a lot by utilizing multi-phase clocks. But I have designed a lot of state machines and I have always been able to do what I needed to do with a single fast clock.

• I totally get your point, but the thing here is that a time-to-digital converter is designed to measure very short periods e.g. less than 1ns. Articles online recommends FPGA or ASIC (for the hardware counter) clocked by a four-phase clock.
– VHDL
May 11, 2017 at 9:21
• That changes things a lot. Intervals of under a nsec are a different animal. I'll be interested to read what you discover. May 11, 2017 at 12:23

For a time-to-digital converter where you want increased resolution in an FPGA, you can use multiple phases and edges. Keep in mind that you can't "just trigger your process" on multiple phases/edges in a real device unless you're using DDR or similarly specialized IO cells, which would defeat the purpose of the internal detection implementation. Instead, you really have parallel timing engines and post-processing to determine the final result based on the output of the different phases. This implementation with parallel timing engines triggered off of 0/90/180/270 degree phase shifts is very similar to 0/90/0-negative/90-negative, but could have subtle differences in how negative-edge triggered flip-flops are implemented in the particular digital design.

I would recommend experimentation with the necessary clocking resources (PLL, routing) and constraints (clock-to-in, synchronizer, domain crossing back to "primary" domain) to see what gives you the best practical implementation.