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I am implementing a DDR3 interface on a PCB and I have a question regarding the termination of address/control/command/clk traces.

I have series terminations for all the required traces mentioned above, my question is whether or not the traces going to these terminations require length matching or should they just be kept as short as possible and left as uneven termination stubs? To me it makes sense to keep them as short as possible even if lengths aren't matched well, but I wanted some other opinions on the matter :)

Thanks!

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  • \$\begingroup\$ depends on track Zo, length and thus propagation delay compared with rise time. if delay is roughly < 16x rise time, then ringing is attenuated, ok, otherwise if delay > 16x rise time then ringing and poor impedance controlled tracks may result in ringing and false values. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 May 11 '17 at 0:13
  • \$\begingroup\$ How many DDR3 chips present? You can refer the JEDEC DIMM specifications for all Trace lengths as a reference. \$\endgroup\$ – user19579 May 11 '17 at 7:21
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I was still unable to find a solid written answer in the JEDEC specification or in design guides but after looking through some reference designs I found that termination resistors are always placed as close as possible to the final signal pin (last ram chip).

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  • \$\begingroup\$ AFAIK length matching is needed to meet timing. \$\endgroup\$ – EE_socal Jul 25 '18 at 23:16
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In short, you don't need length matching for termination resistor traces but you should keep this length minimum, maximum of 300mils is recommended. You can find same recommendation in Micron reference design (I don't recall what exact UG it was, sorry)

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