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Now I'm trying to simulate the performance of Intel CORE 2 Duo processor (but I'll be very pleased with information about any other multi-core Intel processor) and it's work with the computer memory. As I understood, the main problem that exists with memory - is to support the coherence of cache. But how does the protocol MESI work with different layers? For example how does it apply to L2 and L3? I also would be very glad to know enything about non-exclusive write policy implementation and if the replascement algoritm of L2 is connected to the block being replaced from L1? Does Anyone know anything about this?

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    \$\begingroup\$ This is at some level an electrical engineering problem, and we have several experts who could help you with simulating the performance of PIC or Cortex-M3 processor, but this is an unusual question for our site - we may not have the proper expertise for this question. \$\endgroup\$ – Kevin Vermeer Apr 22 '12 at 23:49
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    \$\begingroup\$ Just to clarify - what to you mean by 'performance'? Are you interested in data throughput, power dissipation, or ability to compute some algorithm? Please forgive me if I'm asking silly questions, but this isn't my area of expertise and I'm not sure what you're asking. \$\endgroup\$ – Kevin Vermeer Apr 22 '12 at 23:50
  • \$\begingroup\$ Ok, first of all, thank you for your answer!=) Maybe,it's my mistake that I didnt say that I use the GPSS language for modeling.So,I need algorithms of constructive engagement of cache layers,replacement algorithms (and if they are connected to each other) and how does MESI apply to different layers.I consider cache lines(blocks) with their adresses as transacts in GPSS. \$\endgroup\$ – Alexander Apr 23 '12 at 9:47
  • \$\begingroup\$ @Alexander, these are comments, no answers, Kevin is trying to warn you that this may not be the best place for this question. We probably don't house the expertise you seek. \$\endgroup\$ – Kortuk Apr 23 '12 at 17:33
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    \$\begingroup\$ I think this site might actually be the best one for your question on the StackExchange platform. You are however asking for a very specific information, that even thou a lot of people here can understand your question, few can answer. I'd guess hitting up the researchers from Intel, or some industry conferences (Intel Developers Forum?) would work out for you.. on AMD side, I think what you're asking for is described well in the BIOS Developers Guide for K8/K10s.. \$\endgroup\$ – qdot Jun 5 '12 at 21:34
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I guess your question is about how a coherence protocol extends to multi-level caches. This book is a good reference. Here's my understanding:

Ill take the example of Core i7 (as I'm not very familiar with core 2 duo architecture).

In Core i7 every core has a private L1 and L2 cache, and all cores share a single large on-chip L3 cache. One can in-turn join multiple such processors using point-to-point links to form a NUMA system. So there are 4 levels in the memory hierarchy: L1, L2, L3, Main memory.

There is one coherence protocol between multiple L2's on a chip and the L3. There is a separate protocol between multiple L3's on separate chips. The two are independent of each other. One may use snooping, and other may use directory-based implementation. I think in Core i7, both are directory-based MESIF protocols (F is a new Forward state).

All caches in Core i7 are inclusive. This simplifies the protocol somewhat. As L2 is inclusive of L1, a block that is evicted from L2, has to be evicted from L1 too. Similarly, a block evicted from L3 has to be evicted from all L2s. L3 maintains core_valid bits for each block. A core_valid bit is set if the L2 cache of that core has a copy of the block. This way when a block is evicted from L3, the invalidations need to be sent to only those L2s that have a copy of the block. I guess the core_valid bits also act like a kind of directory. If you have inclusion, only the coherence messages for blocks existing in a lower level cache need to be forwarded to the higher level cache. So the lower level cache acts like a snoop filter.

I'm not sure I understand your question about the non-exclusive policy. Maybe this link will help.

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  • \$\begingroup\$ The link does not work. \$\endgroup\$ – devoured elysium Jun 30 '15 at 14:03
  • \$\begingroup\$ I'm pretty sure Intel's L2 caches are Not-Inclusive/Not-Exclusive of L1d / L1i. You're right that L3 is strictly tag-inclusive, so L3 tags work as a snoop filter (Which cache mapping technique is used in intel core i7 processor?). When a line needs to be evicted from a core, L2 and L1i/d all receive the message, I guess. But this answer quotes Intel's manual as saying L2 is not inclusive in Sandybridge. \$\endgroup\$ – Peter Cordes Apr 12 '18 at 9:58

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