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In which stage is decided the Sigma-delta ADC resolution (number of bits) after conversion? Modulation stage or decimation stage?

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    \$\begingroup\$ It's a combination of many factors. Oversample rate, modulation stage, how much bits do you sample, ... \$\endgroup\$ – Joren Vaes May 11 '17 at 9:00
  • \$\begingroup\$ Show a typical block diagram of what you mean. There are many forms of sigma delta ADC and a generic answer doesn't seem appropriate here. \$\endgroup\$ – Andy aka May 11 '17 at 9:39
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The decimation stage 'creates' the apparent resolution of the converter, that is it outputs 16 or 24 or whatever the width of its output register is.

Both the modulation stage and the decimation stage have the ability to limit the effective number of bits (ENOB) you can get from the converter, that is, how many MSBs are actually useful. ENOB is usually measured by converting a pure sine wave, and relating its SINAD to that of a perfect ADC with ENOB number of bits.

Noise in the modulator will limit the noise floor, distortion in the modulator will create tones that are not present in the input. Both could make many of the LSBs of the output irrelevant.

A properly designed decimation stage will have a higher order filter than the order of the modulator. If it's equal or less than the modulator order, then that could start limiting the ENOB of the whole converter at some output sample rates, quite apart from the modulator.

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