EDITED FOR MORE CLARITY
I'm a bit confused by this
I have a digital signal (actually UART, NRZ) of 70KHz that will be sampled by a ADC. The goal will be to decode this signal, but ADC is used because amplitude measurements will be used too.
The swing will be from 40V (high) to 34V (low) but occasionally, other digital control signals will appear on line (not UART) down to few volts.
I am asking because I try to figure out a more elevate explanation (than empirically one) in selection of (expensive) ADC. There are a lot of limitations such SPI speed, frame to be compatible with CPU, etc.
Now clearly a Nyquist point (2x) will not apply here since decoding will be impossible. We empirically selected (for ADC size calculation) some 10x value of oversampling or somewhere around 700Ksps.
Of course, infinite sample will reproduce the square but as one reply bellow, how far should I go or how to better approach this selection.
Please don't post what I could do, bitbang, GPIO, etc.
This is a clear question for a real problem and I would spend all my points (or buy if possible) for serious answers (no bounty hunters).
Thanks in advance.