# How would a ring oscillator with even number of inverters behave?

Intuitively, I understand that with an even number of stages, the output of the last would be the same logic level as the input of the first, so that the output eventually latches to a certain logic level. Whereas, with odd number of inverters, the outputs switch and the resulting frequency is determined by the gate delay.

However I also read that Barkhaussen's criterion does not apply to non-linear circuits, and cannot be used to evaluate the behaviour of a ring oscillator. If that is the case, how do you explain the sustenance of oscillations in the oscillator? More precisely, what would the transient behaviour be like, that leads to oscillations?

Also, is there a necessary DC operating point that either oscillator converges to in the steady state? Is the operating point "stable" in the case of even and "unstable" in the case of odd stages?

It likely wouldn't do anything interesting.

With an even number of inverters, there should be phase shift through the ring of 0 degrees, but there is no DC inversion at the end of the chain, meaning the circuit should be inherently stable.

Initially you may find that they start up in an unstable state but at some point it will settle down because there will always be one inverter that is slightly stronger than the rest - usually the output node as it would normally be loaded.

If you can guarantee that the output of one of the NOT-Gates is in a defined state ("high" or "low") for some time the circuit will latch a state independent of the types of gates used.

However what if the initial output voltages of all gates is the same level?

This surely depends on the exact types of gates used:

If the input voltage of CMOS gates for example is exactly in the middle between high and low the output voltage is also in the middle between high and low (which can damage the CMOS gate when doing this for a long time).

However as soon as the input voltage of one CMOS gate rises (or falls) a little bit the output voltage is falling (or rising) rapidly.

Using CMOS gates you would therefore in fact latch some logic level because a small rise of the input voltage of the first gate will cause a large rise of the output voltage of the last gate (which is the input voltage of the first gate).

The N=even ring oscillator behaves just like this simulate this circuit – Schematic created using CircuitLab