I came across on this design when I was searching on the internet for BJT switches.
The Ic current is considered less than the maximum allowed sink current of mcu's pin. I was thinking the concept is that when the GPIO would be at low level (0 Voltage, Base-Emitter = 3.3V) the transistor would be at its saturation region and the current would flow throught its channel. On contrast, when the GPIO pin is pulled high at 3.3V, due to biased base (Base-Emitter = 0V) the transistor would be forced off at cut-off region and no current would flow anymore.
The question here is: how much safe is this topology for an mcu? How much better would I implement a similar concept like this? I was looking for an active low switch.