# Non inverting level translator with BJT

I came across on this design when I was searching on the internet for BJT switches.

The Ic current is considered less than the maximum allowed sink current of mcu's pin. I was thinking the concept is that when the GPIO would be at low level (0 Voltage, Base-Emitter = 3.3V) the transistor would be at its saturation region and the current would flow throught its channel. On contrast, when the GPIO pin is pulled high at 3.3V, due to biased base (Base-Emitter = 0V) the transistor would be forced off at cut-off region and no current would flow anymore.

The question here is: how much safe is this topology for an mcu? How much better would I implement a similar concept like this? I was looking for an active low switch.

• looks ok for inverting output, but NOT a non-inverting switch. But remember , no switch can be designed without specs for Vol/Iol and Voh/Ioh Commented May 15, 2017 at 18:47
• The output would be non inverting because when the GPIO falls to zero the collector would offer us 0V with respect to ground. Commented May 15, 2017 at 18:50
• yes with high impedance risk of leakage and shootthru failure from EMI, ESD etc. so NG Commented May 15, 2017 at 18:51
• The only considerations that must be taken account is the maximum collector-emitter voltage, maximum collector-base voltage and maximum sink current of gpio pin and of course the maximum collector current that usually is much bigger than max allows sink current of gpio pin Commented May 15, 2017 at 18:53
• What problem are you trying to solve? Where are you trying to deliver the current that is being switched by this circuit? Commented May 15, 2017 at 18:55

The circuit you propose is roughly OK. The schematic not so much.

This is a common base amplifier. One use of such things is to handle a large voltage with a small voltage. The first resistor at left (use component designators next time) is probably better omitted, depending on what you are really trying to do. Just tie the base directly to the 3.3 V supply. Put a resistor in series with the emitter to limit the current to a safe level for the digital output and the transistor.

One disadvantage of this approach is that you don't get any current gain. All the collector current goes out the input. Make sure the digital output can handle whatever current you want to sink.

There is no danger to the digital circuit driving the input as long as the transistor meets the appropriate specs. Obviously it must be able to withstand 50 V C-E when off. You don't show resistor values so I can't comment on the current requirements.

Here is the circuit I described above:

With IN fully down to 0 V, there will be about 5.5 mA thru R2. This same current, minus a little bit for the base, will also be the collector current. That is still enough to pull the bottom end of R1 as low as the transistor can, which will be a little below 3.3 V. As long as the digital output driving IN can sink 5.5 mA, this will work fine, and you get about 47 V of swing from a 3.3 V input.

• Why do you use R2? I believe that it would be better without it. Obviously the calculated collector current must be as low as the allowable sink current of digital terminal Commented May 15, 2017 at 21:08
• @MrB: R2 sets the current when IN is held low. Without it, things would get damaged on attempt to force the emitter much below 2.7 V. Put another way, this common base amplifier natively takes current as input. R2 is a voltage to current converter so that IN can be a voltage signal. Commented May 15, 2017 at 21:41
• Whoever downvoted this, I'd really like to know what you think is wrong. Commented May 15, 2017 at 22:19
• When the IN pin is held low, if there's a base resistor as the schematic I proposed, there's no need to put R2. The emitter current then would be limited by R1. I believe the only resistor could be omitted is base-emitter resistor. However I tried my first schematic and worked fine without any problem. I try to think what problem may I encounter down the line. Commented May 17, 2017 at 12:14