I have two incoming signals that I want to test the coincidence between. But, I first want to delay all of the signals from one channel by the period at which the signals are being sent (2 ms) and compare the coincidence this way. So basically, I want to store the real-time information for 2 ms and then replay it as soon as it finishes collecting, and continue this process on and on. Is this feasible using an FPGA? I was thinking of using one of the following:
outputA <= inputA after 2 ms;
outputA <= inertial inputA after 2 ms;
outputA <= transport inputA after 2 ms;
but from what I understand, these are only used for simulation? What other method(s) would be better to accomplish such a task? Using a shift register, or something similar?
In my setup, I have two detectors (single photon counting modules) that convert photons of light into a digital signal (3.3V, about 50 ns pulse width). The signals are then being sent to an Altera DE2 board, where they are tested with AND gates for coincidence (note, the signals are being shortened from 50 ns to around 15 to 25 ns beforehand, with internal logic and no timing loss). The clock on this board runs at 50 MHz, which has a rising edge every 20 ns. The laser sends a pulse every 2 ms. The real counts and random noise counts from these detectors follow no clock, so they will not necessarily share a rising or falling edge exactly the 50 MHz clock. Testing the coincidence is not the issue I'm having, what I need to do now is delay one of the signals by the period of the laser and test the coincidence then. Because the laser is so slow, it is impractical to delay the signal phisically (it would require around 1 km of optical fiber). So, I am trying to do this delay through the FPGA itself. Now to rephrase my questions:
(1) Is it possible to maintain temporal accuracy (down to very few nanoseconds) when using a FIFO buffer to delay one of the incoming signals, or will sending the signals into the buffer lose that accuracy and only share rising/falling edges with my clock? (Does the buffer say that block of data is either entirely zero or entirely 1, depending on whether the signal was in a high or low state at the rising edge of the clock when it collects the data?)
(2) How would I begin to write code for such a buffer, is this something I can find a copy of online or would there be any "buffer wizards" that I can create using a VHDL program like Quartus II?