# Unwanted voltages in inverter

simulate this circuit – Schematic created using CircuitLab

At the top is a schematic of an H-bridge that I built. Im conducting experiments where I attempt to use it as an inverter. I built a circuit that drives the mosfets with a modified sine wave waveform. The circuit consists of an astable multivibrator with the two outputs connected each to monostable multivibrators. The output signals look like this:

This picture is from earlier experiment. When I acctually use the signals to drive the mosfets, the amplitude is over 10V. The blue waveform is offset down for clarity.

The blue and the yellow waveforms are applied to mosfets as shown in the schematic above. The idea is to allow current flow through one pair of mosfets, pause, and then drive the other pair. Here is the output as measured by my oscilloscope:

The space between the pulses is longer than intended (the but that is not important for this experiment). This happened when I increased the voltage of the oscillator.

The output looks somewhat satisfactory except for the parts I've circled in red. They occur during the pause in the driving signal (on the edge of the driving pulse going zero). I understand that this is because the current now decreases, I get a voltage with the opposite polarity.

I would very much like to know how to possibly reduce or remove these unwanted opposite voltages. I have searched an answer to this problem but I have not been able to find a solution. I've been told that the diodes should be of help as they provide a path for the transformer primary current to discharge during the time when the driving signal is off. But they still ARE discharging and therefore producing an unwanted opposite voltage.

Any suggestions will be much appreciated!

EDIT: I did as Dave suggested and I reduced the dead time between pulses and added a load (a 100kohm resistor) across the secondary. This is the output:

The output looks the same with or without the load.

## 4 Answers

The driving scheme you are using is not good for the job.

You can't leave the four MOS open in between the pulses otherwise magnetizing current build up will work against power supply through body diodes. Doing so you return the magnetic energy stored back into supply and get 2Vcc overvoltage.

During the pause you should instead leave a low drop mesh ON for current freewheeling.

So you could have both lowside ON during pauses and then alternatively switch on two opposite MOS during drive phases.

• Also, it's possible to have only one lowside MOS ON, current will flow via other lowside diode. Nov 26, 2017 at 9:30
• Yes you are right, but it may sometimes be unclear which is current direction and hence which is MOS to be held ON among the two lowside. More, bypassing diode by ON MOS reduces conduction losses. Nov 26, 2017 at 12:22

That's a lot of dead time between pulses, and that's pretty much what you'd expect to see as a result. The "correct polarity" pulse represents the time during which the primary current is ramping up in the selected direction, and the "wrong polarity" pulse immediately after represents the time during which the current is ramping down to zero again. You're basically charging and discharging the primary inductance with current, and the unloaded secondary voltage reflects the dI/dt on the primary.

Try it with a load on the secondary — the waveform will look quite different!

On a separate issue, note that you are using N-channel MOSFETs on the high side of each of your half-bridges. These MOSFETs are operating as source followers rather than saturated switches, and as a result, will be dissipating much more power than you probably want. You should either use a proper high-side N-channel gate driver, or switch to P-channel devices on the high side.

• The long dead time between the pulses was accidental, but I ignored it because I really thought it has nothing to do with the problem.. I will do as you suggested tomorrow as it is quite late now, but I would be interested to hear why the dead time matters. What should I expect to see if it were shorter? And why is the situation different with a load on the secondary? May 15, 2017 at 21:15
• Dave, could you take a look at my new output. I put a load on the secondary (100kohm resistor) and I reduced the dead time. I put a picture of the output on my question. The output still looks pretty much the same.. Removing the resistor also does not seem to change anything. May 16, 2017 at 18:27
• 100k is not much of a load -- I assume that you intend for this circuit to transfer a significant amount of power, and you're going to need a test load that's roughly the same order of magnitude. The point is, right now you're seeing the effects of the full inductance of the primary winding. If you load the secondary with the intended load, this will mostly disappear, and you'll be left with only the "leakage" inductance of the primary. May 16, 2017 at 19:19
• The purpose of "dead time" is to prevent the switching devices from "fighting with" the inductor current and wasting power. If you zoom the scope timebase in on the trailing edge of one of your pulses, you'll see a roughly sinusoidal curve as the voltage switches from the peak positive value to the peak negative overshoot value. This time represents 1/2 cycle of the transformer's self-resonant frequency. You want your dead time to be about the same -- it should be on the order of a few microseconds at most. May 16, 2017 at 19:23
• I didn't intend to acctually use this circuit to drive any load, I was just experimenting and wanted to see the voltage on the scope. But I still don't understand at all what you mean when you say that the primary inductance "disappears". If it "disappears", how can we possibly step-up voltage? If the primary has no inductance, is it not just a coil of wire? May 16, 2017 at 19:40

In addition to what Dave said,

Overshoot is due to a lack of RF impedance matching on load voltage into a transformer. That is why spikes are sometimes >50% overshoot on +ve pulses. Yet due to Remanence after the asymmetric t for +I * t then -I * t , the -ve pulse has no overshoot.

So you must consider an RF load snubber and Remanence in your flawed signals. Normally conjugate impedance is designed for a snubber but we don't know what you have.

It appears you are drawing a lot of current as I see the rampped voltages during ON time.

Do you have anything connected to the output transformer?

I also wonder if you have a blown FET in one leg. The two sides look very different, I don't expect that.