Verilog loop for multiple always blocks

Question

If I have more reg declared, every reg needs to have his own always block, for example:

output reg[3:0] A;
output reg[3:0] B;
output reg[3:0] C;  

always @(posedge clock) begin
    if(reset) begin
       A <= 4'b0;
    end
    .
    .
    .
end

always @(posedge clock) begin
    if(reset) begin
       B <= 4'b0;
    end
    .
    .
    .
end

always @(posedge clock) begin
    if(reset) begin
       C <= 4'b0;
    end
    .
    .
    .
end

What if I have a loop, lets say something like this:

repeat n times
    if(C<0) begin
         shift C two positions
         C <= C + 1;
    else
         shift A one position
         A <= C + 1;
end

As you see here, inside of if(C<0) block, I can't have

C <= C << 2;
C <= C + 1;

so I will need separate register to store C shifted, let's say it will be output reg[8:0] shiftC, so by the way I need separate always block. And of course, separate always block for A too.

My question is, how can I make this loop work, if I use multiple always blocks? PS: here, number of bits is just informative, and does not matter.

Answer 1

I learned […] every reg needs to have his own always block…

I think you've got this backwards. Each register should only be assigned to by one always block. However, this doesn't mean you need a separate always block for each register! It's perfectly safe (and, in fact, quite normal) to have a single always block for all the synchronous logic in a module, e.g.

always @(posedge clk) begin
    if (reset) begin
        A <= 4'b0;
        B <= 4'b0;
        …etc…
    end else begin
        …etc…
    end
end

What if I have a loop, lets say something like this:

You can't do that in a loop.

Verilog loops are for generating multiple copies of repeated logic. They are not a substitute for clocked logic -- if you need to perform multiple actions, you will probably need to make them happen on separate clocks, and implement them in a state machine.

Depending on what you need to happen, there might be some way to "unroll" the loop and make several iterations happen in a single clock. However, you will need to be very careful about how you implement this. Making multiple levels of branching logic run in a single clock cycle is generally inadvisable; data dependencies will severely limit the clock rate of such a design.