0
\$\begingroup\$

I have a system where multiple electromagnets/solenoids are switched with a high-side MOSFET switching circuit. The switching circuit diagram is as follows: MOSFET switching circuit

As seen from the circuit diagram, the solenoid is switched with an NMOS-PMOS transistor pair configuration, and the control signal comes from a 74HC595 shift register. The NMOS transistor (Q25) is the BSS138L, which has a maximum drain current of 200 mA. The PMOS transitor (Q110) is the DMP2305U, which has a maximum continuous drain current of 4.2 A. All transistors are in SOT-23 package. The solenoid has a resistance of 75 Ohms and draws approximately 150-250 mA of current when switched on. The flyback diode (D25) is the 1N4007. The wires from the switching circuit to the actual terminal of the solenoid vary in length from between 2 to 10 meters. No additional flyback diodes exist at the solenoids, nor is it practically possible to get to the solenoid to add such diodes there (due to the design of the current system). Therefore, they exist on the switching side of the circuitry.

What occasionally happens is the following: After the solenoid has been commanded to switch off, it occasionally stays "stuck" in the on position, even though the output from the 74HC595 is off ("low"). The LED in the diagram is there to indicate what the switching state of the circuit is at any given time. In this case, this LED also remains on, which indicates that (at the very least) the PMOS transistor is still conducting. When the solenoid is commanded to switch on again, the NMOS transistor burns out (with a rather spectacular glow) and the 74HC595 gets fried. The PMOS transistor seems to still be fine, although I wouldn't count on it.

It has been pointed out to me that the flyback diode is probably too slow in dissipating the inductive kickback caused by switching off the solenoid. This can certainly be replaced by a Schottky diode for faster dissipation of the inductive kickback.

The fact that the NMOS transistor and 74HC595 gets damaged suggests that there is probably 12-15 VDC (from VCC) ending up at the output of the 74HC595 (and thus at the gate of the NMOS transistor), which conflicts with the 5 VDC power supply of the 74HC595 and eventually damages the IC. My guess is that what is possibly happening is that the flyback diode cannot dissipate the inductive kickback fast enough and that a large enough voltage differential occurs at the source terminal that damages the internal diode of the PMOS transistor as well as the transistor itself, and essentially short-circuits the gate terminal with the drain/source. Now that this happened, there is a very low resistance path from VCC to the drain terminal of the NMOS transistor via the gate of the PMOS transistor. In addition, there is then also a constant low resistance path between VCC and the solenoid, since the transistor constantly conducts at this stage. When the NMOS transistor gets switched on, it essentially short-circuits VCC with GND (via the NMOS transistor) and damages the NMOS transistor, causing a similar gate-drain/source short-circuit path that ends up at the 74HC595.

In order to prevent current from flowing into the PMOS transistor due to the inductive kickback, I thought of putting a diode in series with its source terminal (D86 in the below schematic). In addition, a low-ohm resistor (R92 in the below schematic) in series with the flyback (Schottky) diode could also help in dissipating the inductive kickback faster. This brings us to the following schematic:Updated switching circuit

Does my analysis make sense/does it seem plausable? Does it sound like a good solution to the problem?

For what it is worth, this question is related to another earlier question I posted but focuses on a separate issue. The issue in my other post and this issue are most likely related in some ways, but I would like to focus on each issue separately. Many thanks to those who already contributed to the other post.

Your help would be greatly appreciated in this regard. Thank you in advance.

=======================================================

UPDATE:

Taking into account all of the comments and advice given, I have updated the switching circuit to include the following:

  • Schottky flyback diode (D1) (SS110 in SMA package) instead of the 1N4007
  • Resistors at NMOS gate (R93) as well as between NMOS drain and PMOS gate/gate pull-up resistor node (R92)
  • Bypass capacitor between VCC and GND near the PMOS transistor (C1)
  • A suitably spec'ed PMOS transistor (Q86) with Vgs,max = ±20 V (the DMG2307L, the previously used PMOS transistor is the DMP2305U with Vgs,max = ±8 V).

This leads to the following circuit: Updated switching circuit

A few questions now arise:

  1. The newly chosen PMOS transistor (DMG2307L) has a higher gate threshold voltage (3 V) than the older one (0.9 V). In the original circuit there was no voltage divider at the gate of the PMOS transistor, which lead to gate voltages exceeding the maximum rating of the transistor. Now the new transistor has a higher Vgs,max which is higher than the supply voltage of the circuit, although I would like to still design in a precaution that the PMOS transistor gate never experiences a voltage too high. Therefore the resistor R92 is added in the above circuit. What would be a suitable resistor choice for limiting the gate voltage to 5 V (which should fully turn on the transistor, given its threshold voltage of 3 V)? Is it really necessary to have R92 if the transistor can handle the expected gate voltages, as if R92 wasn't there (i.e. VCC)? UPDATE - Yes, this resistor is requred. The initial placement of R92 was incorrect. It is now moved between Q1's gate and the node connecting R7/Q86's gate.
  2. Is the addition of capacitor C1 a wise idea? Will it help in suppressing any possible voltage spikes that could occur during switching? If so, what would be a suitable value? UPDATE - Yes, this capacitor is required. Values of 220 uF, 470 uF and 1000 uF will be tried/tested.
  3. Is the Schottky diode (D1) choice a suitable one for this application, especially given it is in SMA package? UPDATE - Yes, it is suitable for this use.
\$\endgroup\$
  • 2
    \$\begingroup\$ @analogsystemsrf, what's the idea of putting the big cap across the solenoid? Is it just for fault-finding? It'd obviously affect the solenoid switch-on/off times and put strain on the PSU. \$\endgroup\$ – TonyM May 16 '17 at 5:42
  • 1
    \$\begingroup\$ Let me be clearer: is the 12-15volt VDD heavily bypassed to the Diodes anodes? As the PFETs turn off, the sharp movement low on the drains will couple thru the bulk to sources, and jerk down on the sources; that movement, which is the 12--15volts, couples thru PFET Cgate into drain of NFET, and thru NFET drain-gate to the shift-register. \$\endgroup\$ – analogsystemsrf May 16 '17 at 5:59
  • 2
    \$\begingroup\$ @analogsystemsrf, sorry it's not much clearer at all. But I can decode it as: put a 1000uF capacitor across the supply, close to the FETs. (You also think that when the output FET is switched on, the voltage transition on Q110 source (from GND to 12..15V) will couple through the Cgs of Q110 then the Cdg of Q25 and onto the shift register output. Can't see how that would burn out the FETs but...) \$\endgroup\$ – TonyM May 16 '17 at 6:57
  • 1
    \$\begingroup\$ Whatever the larger problem here, you should have series resistors between each FET gate drive and the FET gate itself. Try 470 R. You have to remember that the gate presents a capacitive load to what's driving it. So when driving low-to-high, your logic gate has a capacitor across it acting as an instantaneous short circuit. When driving low, it's trying to short a charged capacitor. The resistor limits the current between the driver and the FET gate. Do the same for both FETs. \$\endgroup\$ – TonyM May 16 '17 at 7:00
  • 1
    \$\begingroup\$ OK @TonyM I'm sold on Gate R's . The miller cap pulse feedback is bidirectional from Drain to Gate and the transient noise on this cable could be ground shift for all we know. Time for the OP to do some serious Diff Probe scope measurements or get a big CM ferrite sleeve. \$\endgroup\$ – Sunnyskyguy EE75 May 17 '17 at 0:22
4
\$\begingroup\$

Does my analysis make sense/does it seem plausable? Does it sound like a good solution to the problem?

No, because it doesn't address the basic design flaw....

The DMP2305U P channel MOSFET has a maximum voltage rating between gate and source of +/- 8 volts: -

enter image description here

You appear to be hitting it with anything from 12 volts to 15 volts. This will likely puncture the gate-source region and cause the knock-on effects you describe.

As with any new device you choose always read the data sheet for the maximum ratings.

\$\endgroup\$
  • \$\begingroup\$ @wave.jaco, the missing bit in Andyaka's correct answer is the fix: you can put a 10 K resistor between Q25's drain and R31/Q110-gate. If your 12..15 V rail spec is accurate, the Q110 Vgs will be restricted to -6..-7.5 V. Don't forget to put a 470 R series resistor between the 74HC595 and Q25 gate. \$\endgroup\$ – TonyM May 16 '17 at 8:15
  • \$\begingroup\$ @TonyM I would not recommend this. I would want to know the full range of the 12V to 15V power supply voltage and either go for choosing a P channel MOSFET with adequate rating or add a series 2k2 to 4k7 resistor where you suggest AND have a 5.6 volt zener across R31. \$\endgroup\$ – Andy aka May 16 '17 at 9:00
  • \$\begingroup\$ Yes, you're right, a higher spec FET is a better idea. I did put the condition on the rail being accurate. Personally, I don't put zeners in with these low currents, the actual drop can be a volt or two higher until you're in the mA's of their graph. But a FET with Vds(max) of +/-20 V driven from a potential divider looks favourite to me. If you edit your answer with a proposed solution, I'll upvote. \$\endgroup\$ – TonyM May 16 '17 at 9:33
  • \$\begingroup\$ @TonyM I'm done with this question now. The guy asked for an analysis and I told him he needed to fix the design flaw. Job done! \$\endgroup\$ – Andy aka May 16 '17 at 9:36
  • \$\begingroup\$ @Andyaka: Thank you for pointing that out, I did not realize that. I will certainly choose a higher spec'ed PMOS transistor. The 12-15 V power supply is accurate. To be precise, the current system has a power supply of around 14.5 VDC. I specified 12-15 V just to cover any variance on subsequent installations. Regarding the your suggestion for the Zener diode, do you mean it should be in parallel with R31, and with the cathode to the PMOS side or to the NMOS side? Sorry if it sounds trivial, but I want to make 100% sure I understand you correctly. \$\endgroup\$ – wave.jaco May 16 '17 at 13:05
0
\$\begingroup\$

RECOMMENDATIONS

  • Scrap existing design and use more robust Allegro A2982 8 Channel 500mA non-inverting BJT drivers and allow 1.7V drop for choosing V+
  • Include low ESR decoupling cap on board.
  • Use CM choke on all IO cables or SMT CM choke on board ( low cost)
  • use TP or STP cables for all I/O.
  • Isolate Out cables from any sensor cables. enter image description here

previous answer and comments

{ in addition to @Andy_aka 's fine answer}

I have 4 design suggestions;

  • a) improper clamp diodes b) Vds & Vgs violation from negative spike , c) simplification, d) Pulse loop current noise.

    • In general, put power diode across output to ground for high side driver in reverse polarity so negative spike clamps voltage with diode when turned off. It must handle same current as switch but shorter duration determined by L/DCR

. - you don't need a series diode, just a reverse shunt , D25 to gnd on output.

  • you also don't want R92 , it only creates a -ve spike

    • otherwise your exceed Vds absolute MAX of -20V on Q110 with a LARGE negative spike turning off the solenoid faster.. (in andy's datasheet)
  • if you used just a simple low side Nch power driver with RdsOn ~1 ohm, it would work.

schematic

simulate this circuit – Schematic created using CircuitLab

I stretched schematic only for purposes here to illustrate a point ( as much as practical) that dv/dt and dI/dt generate E and H field EMI from antenna effects.

  • 74HCxxx logic @ 5V is roughly equivalent to a voltage source with a 100 Ohm gate resistor.
\$\endgroup\$
  • \$\begingroup\$ Can you flip that voltage source the right way? Drives me mad. Thanks in advance! \$\endgroup\$ – winny May 16 '17 at 20:26
  • \$\begingroup\$ sure , sorry, It was intentional to simulate a power source off board but wires close together. ( i was using an illogical represent to try and illustrate a physical twisted pair not possible here ;) Students often have inductive pigtails and no decoupling caps with a Big Loop Antenna and wonder why they have glitches. \$\endgroup\$ – Sunnyskyguy EE75 May 16 '17 at 20:40
  • \$\begingroup\$ Thanks. I got the distance part. But without reading everything in detail, isn't it just the inductive kickback from the relay coil itself which kills OPs MOSFET? \$\endgroup\$ – winny May 16 '17 at 20:51
  • \$\begingroup\$ Andy told him about 1 stage overvoltage on 2nd gate. I added kickback part on -Vds overvoltage and then it can be simplified to 1 NchFet and watch out for transient loops for EMI \$\endgroup\$ – Sunnyskyguy EE75 May 16 '17 at 21:11
  • \$\begingroup\$ @wave.jaco are you getting this? \$\endgroup\$ – Sunnyskyguy EE75 May 16 '17 at 23:57

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.