- it can be realized in one inexpensive programmable array logic chip after you design the logic, including counters
they only cost $1 but require free tools and experienced designer to do for you. https://media.digikey.com/pdf/Data%20Sheets/Atmel%20PDFs/ATF16V8B,%20BQ,%20BQL.pdf
assuming these are always RTZ pulses after the burst, and rising edge time is what you need to measure, yes there are many ways to measure time interval of latency on the 1st pulse of each channel and also use that to control the 2P2T flow of each input to two outputs.
Once triggered on the 1st edge , further logic switching is disabled for an interval of say 1/2 second then rearmed to react to way for the 1st pulse from two inputsto control the flow of the next pair of pulses. This requires two clocked FF's to be XNOR'd for a time interval counter and two more FF's to determine the race. Each FF uses the other FF's output into D to judge who comes first.
In case of a tie, (which we call a métastable or race condition) you need another criteria to define the result. like no change in path, from previous burst.
This race condition may be your dilemma, but the rest is straightforward.
But I see a solution with a dual FF , an A or B selectors with at least 2 in, 2 out and an XNOR gate for the Time interval counter pulse with 1/2 second timer to rearm the race detectors which were latched by the previous 1st pulse.
There is no need for analog switches or transmission gates but you can use if you like, just as they are used inside FF's.