library ieee;
    use ieee.std_logic_1164.all;  
    use ieee.std_logic_arith.all;              
    use ieee.std_logic_unsigned.all;

    entity ctrl_unit is
    port(   clock_cu:   in  std_logic;
        rst_cu:     in  std_logic;
        PCld_cu:    in  std_logic;
        mdata_out:  in  std_logic_vector(15 downto 0);
        dpdata_out: in  std_logic_vector(15 downto 0);
        maddr_in:   out     std_logic_vector(15 downto 0);        
        immdata:    out     std_logic_vector(15 downto 0);
        RFs_cu:     out std_logic_vector(1 downto 0);
        RFwa_cu:    out std_logic_vector(3 downto 0);
        RFr1a_cu:   out std_logic_vector(3 downto 0);
        RFr2a_cu:   out std_logic_vector(3 downto 0);
        RFwe_cu:    out std_logic;
        RFr1e_cu:   out std_logic;
        RFr2e_cu:   out std_logic;
        jpen_cu:    out     std_logic;
        ALUs_cu:    out std_logic_vector(1 downto 0);   
        Mre_cu:     out     std_logic;
        Mwe_cu:     out     std_logic;
        oe_cu:      out     std_logic
    end ctrl_unit;

    architecture struct of ctrl_unit is

    component controller is
    port(   clock:      in std_logic;
        rst:        in std_logic;
        IR_word:    in std_logic_vector(15 downto 0);
        RFs_ctrl:   out std_logic_vector(1 downto 0);
        RFwa_ctrl:  out std_logic_vector(3 downto 0);
        RFr1a_ctrl: out std_logic_vector(3 downto 0);
        RFr2a_ctrl: out std_logic_vector(3 downto 0);
        RFwe_ctrl:  out std_logic;
        RFr1e_ctrl: out std_logic;
        RFr2e_ctrl: out std_logic;                       
        ALUs_ctrl:  out std_logic_vector(1 downto 0);    
        jmpen_ctrl: out std_logic;
        PCinc_ctrl: out std_logic;
        PCclr_ctrl: out std_logic;
        IRld_ctrl:  out std_logic;
        Ms_ctrl:    out std_logic_vector(1 downto 0);
        Mre_ctrl:   out std_logic;
        Mwe_ctrl:   out std_logic;
        oe_ctrl:    out std_logic
    end component;

    component IR is
    port(   IRin:       in std_logic_vector(15 downto 0);
        IRld:       in std_logic;
        dir_addr:   out std_logic_vector(15 downto 0);
        IRout:      out std_logic_vector(15 downto 0)
    end component;

    component PC is   
    port(   PCld:   in std_logic;
        PCinc:  in std_logic;
        PCclr:  in std_logic;
        PCin:   in std_logic_vector(15 downto 0);
        PCout:  out std_logic_vector(15 downto 0)
    end component;   

    component bigmux is
    port(   Ia:     in std_logic_vector(15 downto 0);
        Ib:     in std_logic_vector(15 downto 0);
        Ic: in std_logic_vector(15 downto 0);
        Id: in std_logic_vector(15 downto 0);
        Option: in std_logic_vector(1 downto 0);
        Muxout: out std_logic_vector(15 downto 0)
    end component;

    signal IR_sig: std_logic_vector(15 downto 0);
    signal PCinc_sig, PCclr_sig, IRld_sig: std_logic;
    signal Ms_sig: std_logic_vector(1 downto 0);
    signal PC2mux: std_logic_vector(15 downto 0);
    signal IR2mux_a, IR2mux_b: std_logic_vector(15 downto 0);


      IR2mux_a <= "00000000" & IR_sig(7 downto 0);
      IR2mux_b <= "000000000000" & IR_sig(11 downto 8); 
      immdata <= IR2mux_a;

      U0: controller port map(  clock_cu,rst_cu,IR_sig,RFs_cu,RFwa_cu,
      U1: PC port map(PCld_cu, PCinc_sig, PCclr_sig, IR2mux_a, PC2mux);
      U2: IR port map(mdata_out, IRld_sig, IR2mux_a, IR_sig);
      U3: bigmux port map(dpdata_out,IR2mux_a,PC2mux,IR2mux_b,Ms_sig,maddr_in);

    end struct;

I have a vhdl code like above but when i try to implement it, it show error like this: enter image description here

can anyone please tell me what i'm doing wrong here? thanks.

  • \$\begingroup\$ Hint, drivers means outputs of your components \$\endgroup\$
    – sstobbe
    May 18, 2017 at 4:14

2 Answers 2


First off:

use ieee.std_logic_arith.all;              
use ieee.std_logic_unsigned.all;

Baaaad. these are non-standardized libraries (even though they are named "ieee.std"). Instead use:

use ieee.numeric_std.all;

... if required. But in this case you are not doing any arithmetic at all. So why include these libraries??

Next, it is no longer required to define component interfaces in architectures. Instead of:

architecture arch of ent is
    component foo is
    end component;
    inst_foo : foo
        port map (

You can just type:

architecture arch of ent is
    inst_foo : entity work.foo
        port map (

Also, please use full assignment in port and generic mappings: it saves errors when changing the entities. So not:

inst : comp port map (a, b, c);


inst : comp port map (in1 => a, in2 => b, out1 => c);

finally, multiple assignments. For example look at these lines:

  IR2mux_a <= "00000000" & IR_sig(7 downto 0);
  U2: IR port map(mdata_out, IRld_sig, IR2mux_a, IR_sig);

In the second line IR2mux_a is the third argument: that is an output port of the component IR! So the signal IR2mux_a is both driven by the component IR and by the assignment in the first line.


Those signals are assigned values in multiple places. Change the code so they are only assigned in one place. One of them is assigned a value from another signal and it is connected to the output of a module. Pick one. Maybe you need different signals and a much of some sort.


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