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What are some factors considered to ensure a SAR-type ADC is accurate on the hardware level? Some things I think are relevant:

  1. Buffering the ADC inputs
  2. Voltage reference accuracy
  3. Having an accurate oscillator for the processor

Would there be any other major considerations? The assumption would be for someone using any commercially-available SAR-ADC chip and not designing the ADC circuit itself.

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  • \$\begingroup\$ I do not see how 1 and 3 would influence the accuracy. 1) because even without the buffer, it is the input voltage of the ADC which is measured. If the load of the ADC lowers the input voltage then the ADC still gives the right value, of that lowered voltage. Also a buffer could add offset. Not saying not to use a buffer, but saying that a buffer does not influence the ADC's own accuracy. Regarding 3, processors do not need accurate clocks unless these are used for accurate timing. A SAR ADC does not use time as a reference, it just needs "a" clock. Only the ref. voltage needs to be accurate. \$\endgroup\$ – Bimpelrekkie May 18 '17 at 7:11
  • \$\begingroup\$ I would add: clean supplies with plenty decoupling. Low noise supplies, especially for the reference voltage. If the ADC has an internal reference voltage generator, use that. Proper grounding scheme (start ground). Follow the guidelines and schematics from the datasheet. \$\endgroup\$ – Bimpelrekkie May 18 '17 at 7:13
  • \$\begingroup\$ Lets not forget layout, including layout to minimize thermal effects etc \$\endgroup\$ – Dirk Bruere May 18 '17 at 8:28
  • \$\begingroup\$ FakeMoustache - the accuracy of the timing is vital. Poor clock perofrmance (jitter) will ruin the resolution. This is one of the main limiting factors in high-accuracy high-speed ADCs. \$\endgroup\$ – Joren Vaes May 18 '17 at 9:21
  • \$\begingroup\$ @JorenVaes the accuracy of the timing is vital Nope. it is not. You're thinking sigma-delta ADCs. Where it can be an issue. Also jitter and accuracy are different things. A clock can be either 1 ppm precise but still be unusable due to jitter. Most SAR ADCs use a flash converter for speed, then the clock is largely irrelevant. \$\endgroup\$ – Bimpelrekkie May 18 '17 at 9:35
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See this http://www.delftek.com/wp-content/uploads/2012/04/National_ABCs_of_ADCs.pdf

  1. Not directly. Of course, a bad buffer will ruin your digitized signal, adding noise, shifting or gaining slope, clipping, etc.

  2. Of course, speaking about precision. If you have 16 bits and 3V reference, this means 3/2^16 will be 45.77uV. Any ripple more than this value will destroy your ENOB (effective number of bits). In other words, you will have 10 bits of your great and expensive 16 bits precision ADC.

  3. Clock jitter will greatly impact performances as general rule of thumb. For Some external ADCs (SPI for example) clock is internal and not modifiable.

The only thing to take care is jitter of start conversion (CS - chip select) which will impact sampling points precision over time and SPI clock (grabbing data) which in some cases must not overlap acquisition time but it's hard to say, just read particular ADC datasheet.

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One very important point often forgotten: make sure the signal has no frequency component above half the sampling rate, i.e. satisfy Nyquist–Shannon sampling theorem (unless you are intentionally undersampling). So in most cases you need a good low pass filter in front of the ADC.

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Just a quick mention when using SAR ADCs - watch out for the minimum sample rate. Many SARs employ a pipeline architecture and store successive voltages in small capacitors - wait to long for the next clock edge and the leakage current will degrade the accuracy of the readings.

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  • \$\begingroup\$ SARs are a pipeline architecture and store successive voltages in small capacitors Not all SAR DACs are, some have a flash converter so no pipeline and no voltage divisions using small capacitors. \$\endgroup\$ – Bimpelrekkie May 18 '17 at 9:40
  • \$\begingroup\$ Did you mean ADC? Also, I didn't know that, all the ones I've used have been. Out of interest can you link me to a part? \$\endgroup\$ – Tim Mottram May 18 '17 at 9:54
  • \$\begingroup\$ Yes, I mean SAR ADC. I cannot find one with a flash DAC (maybe because I was thinking of a flash ADC) but here's the AD537: analog.com/media/en/technical-documentation/data-sheets/… which has a current DAC which works "instantaneously", similarly as a flash ADC. And also no pipelines and caps. \$\endgroup\$ – Bimpelrekkie May 18 '17 at 10:02
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Buffering the ADC inputs

Don't just slap an unity gain impedance buffer on the output if you don't need the full bandwidth of the SAR. Use a low pass filter with a cutoff at the bandwidth of signal that your interested in. The buffer or LPF can have impedance effects with the SAR inputs. Most ADCs will give you an input impedance equivalent of the ADC's input. You can then simulate this in spice and see what the AC gain of the buffer and the ADC.

Voltage reference accuracy

Use a voltage reference with enough accuracy for the SAR bit depth. Remeber that 1/f noise is a problem with voltage references also, your only as good as your reference.

Another trick is to make sure you have a low impedance pathway between the reference and the ADC, or put a large cap on the reference or use a reference with a kelvin connection (like the LTC6655) to keep the voltage at the same level at the ADC input that is being regulated at the output of the voltage reference. Impedance between the reference and the ADC can be a problem at high frequencies. Do not put other loads on the reference that might create noise, if you do, use an impedance buffer.

Having an accurate oscillator for the processor

This isn't as concerning as actually sampling the SAR, SAR's are fast. You need to make sure the microprocessor can keep up with the SAR at its sampling rate and that the timing is accurate, especially if the microprocessor is initiating the sampling (and not just picking up the data that the SAR is throwing out.)

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Lots of good answers above,

Other important points to consider, is if the inputs are multiplexed and how the sample and hold is implemented on chip. Typically the aperture time is much shorter than the sample period. Depending on the front-end architecture, during the sample phase, you will see a large charge injection.

It is prudent to bypass the inputs the best you can will still maintaining your input bandwidth.

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Adding to the other answers:

Watch out for your source impedance, since it has to charge the internal sampling cap and settle its voltage during the sampling window.

This is important mostly for slow/microcontroller ADC when you try to save power and thus select high resistor values in a voltage divider.

A way to circumvent this is to place a capacitor at the input. This allows higher value resistors to work, but then the frequency of acquisitions should not be too high, because the voltage on the cap has to settle between acquisitions, and the time constant depends on the high value divider resistors...

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Output data transfer requires connecting the ADC parallel output pins to a noisy MCU or bus. That noise, ongoing during conversion, trashes the binary search process, because the Output pins get hit with 100s of milliVolts of MCU ringing at 100MHz or higher. That ringing couples thru the ADC output transistors, isolation junctions, ESD diodes, enters the SAR IC and then explores ALL POSSIBLE paths back home.

Provide buffers to isolate the SAR from the MCU or databuss.

EDIT How bad does this get? +-0.1volt of ripple at 100MHz is dV/dT of 63MegaVolt per second. That slewrate, into 10pF (total capacitance from ADC digital output buffer, bringing the external trash on that digital pin into the ADC), is 6.3e+7 * 1e-11F = 6.3e-4 amps coupled into the ADC.

That current needs an exit path. Consider the ADC GND pin/vias/PCB traces, to have 10 nanoHenry inductance. V = L * dI*/dT = 10nH * 6.3 e-4 amps*radian_freq = 10 e-9 * 6.3e-4 * 630Million radians/second = 36,000 * e-9 e-4 e+6 = (36 e+3) e-9 e-4 e+6 = 36 e-4 = 3.6 milliVolts Ground upset in the ADC.

Can you live with that? At the 8-bit ADC level, probably. Not at 12 bits. Nor at 16 or 20 or 24 bits.

EDIT With 3.6 milliVolts of high speed trash entering circuits by OpAmp CHIP_SELECT pins, or SPI_configuration pins or ADC output interfaces or DAC input_data interfaces, the system/circuit designer must PLAN the interfaces between analog and rf and digital and PowerSupply. FPGAs cause 300MHz ringing of VDD; with 300MHz up beyond the self-resonant frequency of bypass capacitors, I view a RESISTOR in the VDD as essential to success of high-resolution or lownoisefloor systems.

Here is example schematic from the Datasheet for LT2400; notice how C4 has purpose of providing private power to the buffer IC; I'd add a 10 Ohm resistor between the cap and the global +5, to prevent Buffer VDD ringing from becoming ADC VDD ringing.

enter image description here

and here is plot of codespread (at 1/2 ppm resolution, for this 1/8 ppm ADC)

enter image description here

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