Output data transfer requires connecting the ADC parallel output pins to a noisy MCU or bus. That noise, ongoing during conversion, trashes the binary search process, because the Output pins get hit with 100s of milliVolts of MCU ringing at 100MHz or higher. That ringing couples thru the ADC output transistors, isolation junctions, ESD diodes, enters the SAR IC and then explores ALL POSSIBLE paths back home.
Provide buffers to isolate the SAR from the MCU or databuss.
EDIT How bad does this get? +-0.1volt of ripple at 100MHz is dV/dT of 63MegaVolt per second. That slewrate, into 10pF (total capacitance from ADC digital output buffer, bringing the external trash on that digital pin into the ADC), is 6.3e+7 * 1e-11F = 6.3e-4 amps coupled into the ADC.
That current needs an exit path. Consider the ADC GND pin/vias/PCB traces, to have 10 nanoHenry inductance. V = L * dI*/dT = 10nH * 6.3 e-4 amps*radian_freq
= 10 e-9 * 6.3e-4 * 630Million radians/second = 36,000 * e-9 e-4 e+6
= (36 e+3) e-9 e-4 e+6 = 36 e-4 = 3.6 milliVolts Ground upset in the ADC.
Can you live with that? At the 8-bit ADC level, probably. Not at 12 bits.
Nor at 16 or 20 or 24 bits.
EDIT With 3.6 milliVolts of high speed trash entering circuits by OpAmp CHIP_SELECT pins, or SPI_configuration pins or ADC output interfaces or DAC input_data interfaces, the system/circuit designer must PLAN the interfaces between analog and rf and digital and PowerSupply. FPGAs cause 300MHz ringing of VDD; with 300MHz up beyond the self-resonant frequency of bypass capacitors, I view a RESISTOR in the VDD as essential to success of high-resolution or lownoisefloor systems.
Here is example schematic from the Datasheet for LT2400; notice how C4 has purpose of providing private power to the buffer IC; I'd add a 10 Ohm resistor between the cap and the global +5, to prevent Buffer VDD ringing from becoming ADC VDD ringing.
and here is plot of codespread (at 1/2 ppm resolution, for this 1/8 ppm ADC)