# Buck circuit breaking half bridge driver

I have built a dc-dc synchronous buck converter and as seen below

When I turn on the source I have to limit the current the source supplies which is to be expected but if i increase the current limit too high then the half-bridge driver blows. As I understand it, the majority of the current should be flowing through the MOSFETS - either from the 12V source through Q2 to the inductor to the capacitor or in a loop through Q1 with the indcutor and capacitor. Where is current going into the chip and why does it increase as I increase the current limit? Is it occurring at Vs? Will putting a voltage follower into Vs help? Any help would be appreciated.

• Where are the protective diodes for Q1 anf Q2? – Rohat Kılıç May 18 '17 at 14:03
• @RohatKılıç I am not aware of the protective diodes that you are talking about, please elaborate – Alura May 18 '17 at 14:11
• Put some high voltage-low current fast diodes across each MOSFET to protect them against the spikes caused by inductive component of the load. Perhaps this will not help the excessive current consumption issue but is essential. – Rohat Kılıç May 18 '17 at 14:16
• Are you sure that the circuit works correctly even with current limiting? Seems a bit odd to me, because bootstrapping may not work. Hope I'm wrong. – Rohat Kılıç May 18 '17 at 14:20
• How do you soft start and bootstrap the highside? – winny May 18 '17 at 14:27

## 2 Answers

Do an impedance graph of source bridge and RLC Load then apply fourier spectrum of signal to understand why the losses are excessive.

With resonance near 0.1 Hz and Z(f) a few mOhms, your ESR is real load of 20mOhms.

So driver's RdsOn must be a few % of this and probably needs 2 stages of drivers to obtain this speed. which is far too high!!

6mOhm(2SK3069) / 20 mOhm(load ESR)is 20% of load is very inefficient.

What you need are better design specs. Currently we see NONE.

If the SuperCap is rated for 20A at 10'C rise then you need a battery charger rated for this current and Cap cell voltage safe limit e.g. 2.5~ 2.7V with cell balancing if operating in any series string.

No offense, but this is a Mickey Mouse Design.

Which Cap spec do you have?

Well well... first, review of the design:

• MOSFET choice: bad. No need for a 60V FET since you use 12V. Get a 20-30V FET with better RdsON*Qg. Also try more modern FETs. Cannot give recommendations since you do not tell us the CURRENT you want...
• Driver choice: very bad, since this is a low-strength (130mA) driver for high voltage FETs. Use a lower voltage driver with lots more gate drive current like ADP3120 or its more modern variants.
• Inductor choice: unbelievably bad, it is 1000x too large.
• BOOT cap: should be large enough to actually charge the FET gate! This one has more than 1nF Cgs so voltage on your 1nF Cboot will collapse on switching and it wont work.
• BOOT diode: I suspect it is the wrong type but no data provided.
• Layout: I am afraid to look at it.

Now, I am going to bet that your driver blows because you did not put decoupling caps on the input power rail, so when the top MOS turns ON and attempts to draw output current from the power supply, wire inductance combined with di/dt make the power rail voltage crash and burn then become negative until the driver acts as a diode.

• agreed but any design review starts with specs. Buy any 20A low voltage battery charger with set V and I limit would be better. This switch design is limited to about 10% PWM which is insufficient for 20 mOhm ESR Supercap. With ESR*C<20m*200F=4 seconds will have a secondary memory T which causes memory effect so LC values are about right but f can be reduced to 20kHz with RdsOn <1 mOhm to make it work. but 1.8mH DCR must be reduced to same low level thus much lower L. – Sunnyskyguy EE75 May 18 '17 at 17:38
• Better approach is a centre tapped core to prevent DC flux saturation of core with variable ripple current thus not a single half bridge but two drivers. Otherwise Your Choke may overheat from a short circuit 0V on Cap from max current nearing saturation with DC remanence. – Sunnyskyguy EE75 May 18 '17 at 17:51