I am trying to develop a digital data link based on FPGA (spartan 3E) where the transmitter serializes 8 bit parallel input to single channel. At receiver side I want to get the data back by de serializing. I am not adding clock recovery complexity at this point. I can serialize the data at transmitter side where the 8 bit input can be multiplexed using a simple counter. I want to understand how to demultiplex the signal at Rx side. How can I control the Rx when to start demultiplexing data, so that I can get exact 8 bit parallel output as sent at Tx input side. Please let me know if you need any other information.
For a low speed serial communication you can send data, clock, and frame sync. The first two are obvious. The frame sync signal can be sent in several ways, at the start of each 8-bit packet, or at its end. On the receiving side, if the frame sync is sent at the end of the 8-bit packet, it can be used as a latch enable signal on the serial to parallel converter in the receiver
In serial links you have hardware at both ends called a SERDES block (serialiser-deserialiser). The role of the SERDES block is to ensure that data is multiplexed into the stream at the right point, and data is demultiplexed from the stream at the right point.
The TX side is quite straight forward as you have determined. There are two options that come to mind:
- A counter and a multiplexer. Count from 0 to n and feed that into a mux to select the data. A pipeline register on the output would be useful.
- The other more typical way is a simple shift register with parallel load, serial output.
I would suggest the latter because it will be easier for the design to meet timing at higher frequencies, and also use less resources as the Spartan 3Es can build shift registers in RAM.
For the RX side things are more tricky. You need to be able to determine which bit is the first bit in the stream. For this again there are three typical ways:
Using a specific packet format, such as UART (RS-232). There would be long period of the "stop" bit, and then resynchronisation occurs when a "start" bit is detected.
Using a synchronisation signal. For example you can have an extra signal which is typically known as a "Frame Clock" which has a period matching the parallel data rate (i.e. serial rate / n).
Using a process called "Link Training" or "Alignment" whereby at the beginning (after the design comes out of reset) you continuously send a data value known to both sides of the link known as a training word (e.g. 4'b11110000)
For the first example I will leave you to refer to the workings of UART. This process is ok for small bursts of data, but for long continuous streams it is easy to get out of sync.
In the second example your receiver can use the frame clock directly to determine which is the first bit. For example if your transmitter sets the frame clock high only for the first data bit, then whenever the receiver sees a high signal it knows that the current bit is the first bit.
In the third example, the transmitter will send a continuous stream of the training word. The receiver when it comes out of reset will look for this word by performing an operation known as "Bit Slip" - essentially it changes the alignment of the data in the receiver shift register. The receiver keeps performing bit slip operations until it the data it is receiving matches the training word. It then either signals back to the transmitter that a link is established, or the transmitter is set to stop sending training words after a specific number of cycles.
FPGAs also typically have some form of SERDES block built into the periphery (near the pins). If the Spartan 3E has such blocks you can use them to form the basis of your link.
The SERDES block will typically have on the transmit the required hardware for serialisation of a parallel bus, and on the receive the opposite (deserialization hardware). If the FPGA is advanced enough you will probably find the SERDES block will also have a bit slip control signal.