In Verilog, is it ok to use negedge of clock. Can a memory element be triggered at the negedge of clock? How robust will be the design practically in the chip?
Internal memory blocks (e.g. M9K) are clocked at positive edge of the clock, thus they will do nothing on negative edge of the clock.
But you can feed inverted clock to the M9K block's clock input. For example, you have circuit built using
always block which uses
posedge of the clock to set memory address, data to write and control signals, and then, on following negedge, if you feed the same clock inverted into RAM block, RAM block will sample its input wires (address, data, control) and perform requested operation. I would view this type of operation as "waterfall" (not sure if there's any special term for it).
But there're downsides of it:
- half period of clock must be long enough to have RAM input lines stable; e.g. in my experience for M9K single 1024x9 block I had configuration working properly at 8.8 ns clock, but two blocks combined did not work properly, thus I had to extend clock cycle twice;
- data read from the RAM may appear not on the next rising edge of master clock, but in the second rising edge (because RAM operation is delayed half-clock). Again, if half-cycle of clock is long enough for RAM to retrieve its contents within time of half of the clock, you can sample data on next master clock rising edge, if not, you must have one spare cycle;
- inverting clock at the input to RAM block will introduce very small delay, you should also take it into account.
If you have other devices rather than M9K blocks in mind, then you should refer to their datasheets and timing.