I can synthesis the verilog design in Xilinx Vivado (Webpack) and get the LUT/FF usage from the synthesis report. However, I'd like to estimate the chip area (in mm2) under certain ASIC (not FPGA) spec (for example in 22nm process).
Some articles claim that they got the area with Synopsys Design Compiler, which I cannot access to.
So are there any tools that I can use to estimate chip area from (synthesized) verilog design?
After some research, i tried qflow 1.1 with
osu035 standard cell library for the following verilog code:
module test( input a, input b, output c ); assign c = a + b; endmodule
qflow synthesize place,
synth.log gives following area data:
---------------------------- Total stdcells :4 Total cell width :2.08e+03 Total cell height :8.00e+03 Total cell area :4.16e+06 Total core area :4.16e+06 Average cell height:2.00e+03
But I have no idea which is the unit of the result.
osu035_stdcells.lef contains following lines:
UNITS DATABASE MICRONS 1000 ; END UNITS
Therefore, my best guess is the chip area is
4.16e+06/1000/1000=4.16 micron^2 or
4.16e-6 mm2. It that right?