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I can synthesis the verilog design in Xilinx Vivado (Webpack) and get the LUT/FF usage from the synthesis report. However, I'd like to estimate the chip area (in mm2) under certain ASIC (not FPGA) spec (for example in 22nm process).

Some articles claim that they got the area with Synopsys Design Compiler, which I cannot access to.

So are there any tools that I can use to estimate chip area from (synthesized) verilog design?


Update:

After some research, i tried qflow 1.1 with osu035 standard cell library for the following verilog code:

module test(
    input a,
    input b,
    output c
);

assign c = a + b;

endmodule

After qflow synthesize place, synth.log gives following area data:

----------------------------
Total stdcells     :4
Total cell width   :2.08e+03
Total cell height  :8.00e+03
Total cell area    :4.16e+06
Total core area    :4.16e+06
Average cell height:2.00e+03

But I have no idea which is the unit of the result. The osu035_stdcells.lef contains following lines:

UNITS
  DATABASE MICRONS 1000 ;
END UNITS

Therefore, my best guess is the chip area is 4.16e+06/1000/1000=4.16 micron^2 or 4.16e-6 mm2. It that right?

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  • 2
    \$\begingroup\$ Synthesis tools are very specific to the technology being targeted. The results from an FPGA tool will not be at all applicable to an ASIC target, except maybe as a very rough estimate of relative complexity. If you can't use Synopsis, there are open-source tools you could use, but they might not cover a particular process. \$\endgroup\$ – Dave Tweed May 22 '17 at 11:51
  • \$\begingroup\$ @Dave Tweed: In my case, a rough estimation is enough. So I'd like to know which open-source tool gives proper rough estimation. \$\endgroup\$ – lyu May 22 '17 at 23:24
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The only way to get a really good estimate is to actually run the design through the proper ASIC flow for the process in question. Yes, this requires extremely expensive software, component libraries, proprietary fab data, etc, etc.

You might be able to get a ballpark estimate by synthesizing to gates (not LUTs) with some other toolchain (perhaps even an open source one) and then multiplying gate count by the cell size for the process you're interested in. Note, however, that certain optimizations to utilize FPGA LUTs and other features won't necessarily work well/at all in an ASIC. This also won't work for designs that use FPGA block RAM or large ROM lookup tables without doing some extra work to exclude the RAMs/ROMs from synthesis as gates and then work out the area of each RAM/ROM individually and add it all up.

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  • \$\begingroup\$ A rough estimation is enough. I'd like to know any proper open source tools for a rough estimation. \$\endgroup\$ – lyu May 22 '17 at 23:21
  • \$\begingroup\$ Yosys might be a good option. \$\endgroup\$ – alex.forencich May 23 '17 at 14:38
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You are on the right track. Once qflow has generated a .def file for you, you can view that DEF file in any layout viewer capable of reading DEF format files ("magic" is the layout editor/viewer used by qflow). A layout viewer makes it much easier to find the size in physical units. But yes, the DEF file is in microns, and you can figure out the size of the design from the DIEAREA line at the top of the DEF file (which has format (llx, lly) (urx, ury)).

But, to get a value for a 22nm process, you need to set up qflow for a 22nm process, which means you need to have various file formats for a standard cell set in the target process, mainly liberty (.lib) files and LEF (.lef) files (technology information and standard cell macros, which may be in separate files). Assuming you can get that set up in qflow, you still need to make sure qflow can route the design, because if the logic is too dense, the design will have to be padded out with some percentage of filler cells, and that will increase the design area.

There are other considerations, too, such as how much drive you want outputs to have (based on the length of the route from source to receiver and the input capacitance at the destination), whether you want inputs and outputs to be buffered or double-buffered. The larger the design, though, the less percentage of the area is devoted to I/O, so the less effect these kind of considerations will have on the layout area estimate.

If you can make reasonable judgement calls about loads and fanout and such, then you can get a reasonable area estimate. But the main thing is you have to have a standard cell set, because the area can easily change by a factor of two just depending on how compactly the standard cells are laid out, and what logic functions are available in the set.

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  • \$\begingroup\$ Does Xilinx really call their files "liberty files"? \$\endgroup\$ – Dmitry Grigoryev Aug 3 '17 at 8:38
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    \$\begingroup\$ The liberty (".lib") file format was created by Synopsys but is an open definition, human-readable format that has become ubiquitous in digital synthesis. It defines the timing characteristics of each digital standard cell, the direction and use of inputs, and how to estimate wiring delays. It is complementary to the LEF format (from Cadence, also a human-readable format), which describes the physical geometry of each standard cell. A ".lib" and a ".lef" file have more or less all the technology information you need to synthesize, place, and route a digital circuit. \$\endgroup\$ – R. Timothy Edwards Aug 4 '17 at 13:08

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