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I am about to design my first PCB as part of my graduation project. Of course, as the first step, I try to learn as much as possible. A part of the research I found this 3 part article, that suggests that it is not neccessary and in some cases is even harmful to split the ground plane into analog and digital part, which contradicts what I had learned from the prof. I also read all threads on this site that are concerned with the ground planes/pours. Although majority concur with the article, there are still some opinions that advocate split ground plane. eg

https://electronics.stackexchange.com/a/18255/123162 https://electronics.stackexchange.com/a/103694/123162

As a PCB design novice, I find it confusing and hard to decide who is right and which approach to take. So, should I divide the ground plane into analog and digital parts? I mean physical division, either with a PCB cut or having separate polygons for DGND and AGND (either not connected, or connected in one point)

Perhaps to enable you to make a recommendation, that is tailored to my prospective PCB, I tell you about it.

The PCB will be designed in the free version of Eagle=> 2 layers

The PCB is for testing and precise measurement (current & voltage) of lithium batteries. The board is to be controled from Raspberry Pi over digital interface (GPIO/SPI (40 kHz)). There will be 3 data converters on board (AD5684R, MAX5318, AD7175-2),and connectors for a prebuilt RTC module on the digital side. Analog power comes from external regulated power supply over onboard LT3042 voltage regulator (5.49 V). Additionally there is LT6655B 5 V voltage reference. Analogue part is essentially a DC circuit, the only really HF is internal 16 MHz master clock of the ADC.

Digital 3.3 V (mainly for powering of the digital interfaces) will be sourced from Raspberry PI. Thus, there will be 2 ground connection: external power supply and to digital interface of Raspberry Pi.

In this connection another question: referring to Figure 3, how do I make sure that return currents from the digital interfaces flow to the right ground connection (remember I have 2 of them)?

Additional concern: could the power distribution curcuit disturb sensitive measurements? I was going separate them by routing power on the bottom layer, but that is no longer a good idea in case of monolithic ground plane

And while I am still at asking: Assuming more or less monolithic ground plane on the bottom and signal/component layer on top, what is the best way to connect the negative side of bypass capacitors to the ground plane?

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  • \$\begingroup\$ Do you regulate to 5.49 V because you read that the IC can handle 5.5 V? \$\endgroup\$ – pipe May 23 '17 at 8:31
  • \$\begingroup\$ @pipe 2 reasons: provide dropout headroom for 5 V voltage reference (perhaps should have mentioned it in the post). And increase linear operation range of the (internal) output buffer of the DAC. \$\endgroup\$ – Andrey Pro May 23 '17 at 9:01
  • \$\begingroup\$ I went into this subject in quite some detail a while ago; see electronics.stackexchange.com/questions/185306/… \$\endgroup\$ – Peter Smith May 23 '17 at 11:09
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    \$\begingroup\$ Normally I tell everyone not to split ground planes. But if your professor is an advocate of splitting, you should seriously consider splitting. But pay attention to the GND plane currents as others are saying. \$\endgroup\$ – mkeith May 24 '17 at 4:45
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You got to think in terms of shared impedance (not resistance, really impedance).

Consider the parts of the circuit that use GND as a 0V reference for sensitive analog purposes. Obviously you want each of these "0V references" to be at the same "0V" potential. However current running through the GND plane will introduce an extra error voltage on top of each chip's "0V".

Now draw a schematic of your GND, with the currents running through it.

If you do not split the plane, but you have high currents running through it, because you put the power input connector on the left side, the power output connector on the right side, and the super sensitive analog bits in the middle, then you might have a problem due to high current flowing in GND and creating a voltage gradient.

Depending on frequency, consider impedance (ie, inductance, not just resistance).

Now, there are several solutions to this.

  • You could put your power connectors in more reasonable places (ie, power input next to power output) so the high currents do not travel in your GND plane. This applies to all current loops which carry large, noisy, or high di/dt currents, like the internal loops of a DCDC, or the loops between it and its load (say, a cpu) or even the ground path between a decoupling cap and the chip it decouples.

Make sure you know where these loops are! Order them by troublesomeness (roughly "area * di/dt" for AC or "area*I" for DC). Placement is essential. A good placement with tight current loops makes layout much less of a headache.

  • You could use differential amplifiers and ADCs which ignore common mode noise.

This is mandatory if the voltage to sense sits on a high-side current shunt. Now let's say you use a current sense amp for example. Dont forget whatever voltage is on its "output reference" pin (often mislabeled "GND") is directly added to the output... so dont stick the sense amp between two MOSFETs with its "GND" pin in the middle of the "motor current return" path...

  • You could also split the plane, but then you need to decide where you gonna split it. And (this is where things get nasty) where you link your two grounds together at DC (or at high frequencies if you use isolators...

Let's name your two grounds AGND and PGND (analog and power). Some say to split, and join AGND/PGND or AGND/DGND under the ADC. This means any current that runs between AGND and PGND has to flow in the ground link under the ADC now, which is the worst possible place.

A solution that makes lots of sense is the "hidden split". Placement is essential. For example you put the power/noisy stuff on the right, and the sensitive stuff on the left. You place your decoupling caps so the supply currents loops running through GND are short and well placed. Then, since your board has two well defined zones, you can narrow down the width of ground plane connecting them, to ensure high currents do not run in the sensitive bits' ground.

It's very visual and difficult to explain, and placing your connectors properly is essential.

These tutorials are good: https://learnemc.com/emc-tutorials

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  • \$\begingroup\$ Very good answer. I'll look into your linked tutorials. \$\endgroup\$ – bitsmack May 23 '17 at 1:17
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    \$\begingroup\$ Just to make sure you understood me correctly: when I wrote "split ground plane", I meant physical division, either with a PCB cut or having separate polygons for DGND and AGND )either not connected, or connected in one point). I will add this clarification to the post. \$\endgroup\$ – Andrey Pro May 23 '17 at 7:41
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Simply introducing SLITS into the GND plane may suffice to largely keep digital/power/relay/motor trash out of the delicate analog areas. [ EDIT June 9 Showed a narrow region will achieve 12dB/square attenuation. EDIT June 2019 Remember to slit the Power Plane as well (suggested by barleyman)]

schematic

simulate this circuit – Schematic created using CircuitLab

What can we predict about slit placement versus intrusive-current In point and Out point?

schematic

simulate this circuit

What to expect, as the slit intrudes into currents?

schematic

simulate this circuit

We had approximately 40 microvolts/square along bottom edge of the PCB, assuming 0.0005 Ohms/square. We can estimate the I*R voltage drop, caused by ONE AMPERE at top right of PCB, along the very bottom edge of PCB inside the analog region as simply

Slit_Atten = length of slit / entire loop length inside the sensitive region

Voltage drop at very bottom (per square) is

Voltage across slit * Slit_Atten

Math: slit is 4 squares, thus 4 * 40uV = 160uV.

Slit_Atten is 4 squares / 20 squares (entire loop periphery) = 20%.

The per_square I*R drop is 160uV * 20% = 32 uV.

This shows the value of using only NARROW regions between digital/noise and analog.

Here is another way to slit.

schematic

simulate this circuit

Voltage per square where OpAmps need quiet GND = 32 uVolts, per square. Not very quiet. What to do?

1) cut the slit further into the planes; now at 80%, go to 95% and likely get an exponential improvement in quietness; run the SPICE sim and see how

2) make the slit ----- not narrow ---- but deep, like this

schematic

simulate this circuit

What can we predict about the attenation of "L" slits? Turns out we can predict 12 dB attenuation per square of the narrowed-region. We zoom in, and see this

schematic

simulate this circuit

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    \$\begingroup\$ You know I tried your “simulate” link just because I wonder what it does. \$\endgroup\$ – JDługosz May 23 '17 at 6:27
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    \$\begingroup\$ Slits also turn your PCB into a nice dipole antenna \$\endgroup\$ – Voltage Spike May 23 '17 at 17:37
  • \$\begingroup\$ Notice a smartphone is one integral shielded box, with internal power. And the smartphone camera produces excellent results, in that shielded box with internal power. Have the same mindset for projects needing outside sensors and outside power? \$\endgroup\$ – analogsystemsrf May 24 '17 at 12:41
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    \$\begingroup\$ You don't have "six" paths, you have essentially an unlimited number of paths. Doing 2D field analysis would tell you how the current density behaves more or less realistically. The bottom line is that the current drops fast the farther you go from the primary loop. In real life scenarios, current loops are your enemies i.e. if you have a SMPS circuit in one end and a power hungry circuit at the other end, everything in-between is subject to return current noise in the GND plane. You can indeed mitigate this by using the slots but do not forget to slot your power plane as well. \$\endgroup\$ – Barleyman Jun 7 '17 at 14:36
  • \$\begingroup\$ @ Barleyman Thank you. Note added, at start of anwer. \$\endgroup\$ – analogsystemsrf Jun 11 at 14:49
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The real key is ALWAYS placement, do this intelligently and either setup can work for something like this, get it too badly wrong and not only will the board be very hard to route, but it will be hard to get the precision you want.

Solid planes rule when you have fast stuff going on, anytime you have edge rates in the few ns region (Clock rate does not matter, edge rates do), you want a solid plane under at least that region, I generally do a solid plane in the first prototype every time and mess about with it later if it does not get me what I want (I generally do not need to change it).

Now in your case DC accuracy matters, and generally such things are best done with differential sensing (Decide which two points you want to measure the voltage between and measure that voltage, not the one relative to some plane).

Just because you have a plane does not mean that you need to connect to it at arbitrary points you can for example decide to return the 'grounded' end of a resistor in a differential amp to the plane at the same point as the previous stages input divider resistor, thus ensuring that they see the same voltage, hierarchical grounds are a good thing, but differential measurement rules for this stuff.

5.49 seems optimistic to me, abs max is not somewhere you ever want to be.

Decouplers generally go directly to the plane.

If you decide to split planes, then you must ensure that there is a continuous connection under the area where the control lines pass between the two, you never run any trace over a split in the plane.

Given your low speeds, don't forget that you can over sample, and that decimating extends your effective word length.

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  • \$\begingroup\$ I don't see a problem with the voltage: 5.5 is max operating voltage, abs max are even higher. \$\endgroup\$ – Andrey Pro May 23 '17 at 10:55
  • \$\begingroup\$ Concerning the last paragraph, I utilise delta-sigma ADC, which does it for me. The OP now mentions the models. \$\endgroup\$ – Andrey Pro May 23 '17 at 10:58
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    \$\begingroup\$ If 5.5 is max operating then ok, but if you are targeting 5.49V you may want to work out worst case tolerance on your trimming resistors... Delta sigma decimates a lot, but especially if you only want a few measurements a second you can further reduce the bandwidth to reduce the noise further. Processing gain is real gain. \$\endgroup\$ – Dan Mills May 23 '17 at 11:07
  • \$\begingroup\$ I've got 0.1% 54.9k thin film SMD resistors. \$\endgroup\$ – Andrey Pro May 23 '17 at 11:18
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Some notes on this. As others have pointed out, current loops are not your friends. You should be aware of your high power / high speed circuits and where the power is supplied to them. Anything in-between these two points are directly in the field of fire, don't put your 16-bit ADCs between boost converter and high-power PWM controlled LEDs..

Splits or moats in ground planes can be beneficial but these get involved fast. Most important thing to remember is to NEVER EVER CROSS A SPLIT IN THE PLANE WITH A HIGH-SPEED / SENSITIVE SIGNAL LINE. Your signal lines need a return current path right next to them. So if you create a horseshoe around an ADC, you have to then route all signals around that moat as well. If you absolutely have to cross a split, you could use a local capacitor to link separate GND planes but then you're defeating the purpose of the moat in the 1st place. Presuming you've got a multi-layer board but it'd be much less painful just not to do it. Swap layers before the split to another plane that has uniform reference plane. NB this does not apply to DC or low frequency signals/loads. They're happy enough to follow path of least resistance around the moat. Don't forget you have to match splits in GND planes with matching splits in power planes!

To make this more complicated this applies to the reference plane i.e. ground plane next to the signal layer. If you've got 8 layers or more, it doesn't matter what's on L2 plane if your sensitive circuit is on L8. You can use power plane as a reference as well but often these days you have any number of power planes (5V, 3.3V, 1.8V, 1.2V, -5V, whatever) so the offending circuitry can only be referenced to the power plane it originates from.. Referencing a 1.8V PHY to 3.3V plane won't work. Unless, you know, you provide those stitching caps again between planes.

I have done high-speed ADC multiplex circuit that achieved essentially zero noise (~0.6 ADC unit) level by splitting VCC and VCCA plus GND and AGND. But I know what I'm doing and I spent time religiously mapping analogue lines and creating "islands" of related copper on the next layer and so on. Most of the time I just keep all the grounds together and mind the current loops.

Changing layers also counts as a split in the plane so you should have a matching GND via(s) nearby so the high speed return current won't have to make extra detours.

Final note: Return current follows the path of least resistance. For low frequencies that's the shortest available solid copper route that may not follow your signal/power trace. For higher frequencies its right next to the driving signal as separation increases impedance. That's why crossing planes ends in tears as you're creating discontinuity that results in reflections, radiated RF frequencies, signal integrity loss, rain of frogs and so on.

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    \$\begingroup\$ If one needed wires for sensor with a high-speed data to cross a moat, could one safely do so by running all wires for that sensor, including its ground, as a parallel group and avoiding any connection between the sensor-end of that group and the digital ground plane? \$\endgroup\$ – supercat Jun 7 '17 at 15:08
  • \$\begingroup\$ @supercat That's what I mean by creating ground "islands" for the sensitive analogue traces. You bring your AGND with you under/above the signal traces. And, yes, you'd have to sequester the power for the sensor as well or you make things worse. This easily gets rather convoluted which is why there are cautions against creating slots. When I have separated AGND/DGND I also have a separate low-noise LDO and have the AGND/DGND bridge at the LDO. Analog stuff would be on the underside and digital stuff on the top side of the PCB with copper AGND islands for excursions to other planes. \$\endgroup\$ – Barleyman Jun 7 '17 at 15:20
  • \$\begingroup\$ I was thinking about situations where certain sensors or transducers might need to be located at certain positions on a multi-layer board, and power--along with everything else--would be sent using a group of close parallel traces on one or more layers not used for planes. As long as no tracks on other layers are close to and parallel to the tracks feeding the sensor, I would think that having all currents confined to that strip would limit noise coupling elsewhere. \$\endgroup\$ – supercat Jun 7 '17 at 17:30
  • \$\begingroup\$ Regarding return paths, the charges explore all possible return paths proportional to conductance at the frequency of interest. All possible paths; whether on silicon or in packages with 8 leads or 200 leads or on PCBs with one continuous plane or on PCBs with 5 planes or in systems with 10 PCbs, all possible paths are explored by the charges. \$\endgroup\$ – analogsystemsrf Jun 7 '17 at 17:44
  • \$\begingroup\$ @supercat perfectly valid strategy but you need to use two layers. Put the return ground on a copper strip on one layer and the signal traces on an adjacent layer. And you don't want some noisy "stuff" on the other side if you're using inner layers for the signals. You can also pull signal and return gnd in parallel like differential signals, especially for 2 layer board with large separation between planes. \$\endgroup\$ – Barleyman Jun 7 '17 at 18:08
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You could completely separate power and ground for both analog and digital. Use isolated DC-DC converters and opto-isolation for the digital interface between the two.

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protected by Community Jun 12 '17 at 10:33

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