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I'm trying to write one main module and one as secondary (called "adder"). However, I kept getting errors either telling me there are syntax errors with the "adder". Please help me with my code:

Here is the implementation of the module:

module adder(
output reg [3:0] S_out,
input [3:0] S_in,
input [3:0] coin
);
initial begin 
assign S_out = S_in + coin;end
endmodule

and here is the main module:

module Assign2(
input Nickel,
input Dime,
input Quarter,
input Start,

output reg Release_Paper,
output reg Return_Coins
);
`include "adder.v"//this line is removed 

wire CLK;
CLoK C1(CLK);
reg [3:0]S_in;
reg [3:0]S_out;
reg [3:0]coin;

wire [2:0]i;
assign i = {Quarter, Dime, Nickel};

wire reset;
parameter S0 = 4'b0000;
parameter S1 = 4'b0001;
parameter S2 = 4'b0010;
parameter S3 = 4'b0011;
parameter S4 = 4'b0100;
parameter S5 = 4'b0101;
parameter S6 = 4'b0110;
parameter S7 = 4'b0111;
parameter S8 = 4'b1000;
parameter S9 = 4'b1001;
assign reset = Start;

always @(posedge CLK) begin 
if (reset == 1) begin
    S_in = S0;
    S_out = S0;
end
case(i)
    3'b001: coin <= S1; 
    3'b010: coin <= S2;
    3'b100: coin <= S5;
endcase
#100;
adder jjjjj(.S_out(S_out), .coin(coin), .S_in(S_in));//here is the error
if (S_out == 4'b1010) Release_Paper <= 1'b1;

else if (S_out > 4'b1010) Return_Coins <= 1'b1;
end 

endmodule

EDIT: I have removed the include and here is the error message: [HDL 9-806] Syntax error near "addr". ["....Assign2HDL/Assign2.v":66]

The platform is Xilinx Vivado 2017.1, and I also tried on Xilinx ISE 13.4, which strangely has some issue with my clock:

Line 28: Non-constant loop condition not supported for forever

and here is the clock:

module CLoK(
output reg CLK
);

initial begin
   CLK = 1'b0;

   forever
      #2 CLK = ~CLK;
end

endmodule
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  • \$\begingroup\$ Post the EXACT error message. Try your code on other simulators on edaplayground; you may get more helpful errors there. \$\endgroup\$ – toolic May 23 '17 at 12:31
  • \$\begingroup\$ Do not include the adder file inside the Assign2 module. You could move the include line above the module Assign2 line. \$\endgroup\$ – toolic May 23 '17 at 12:32
  • \$\begingroup\$ @toolic I have removed the include and added additional information above, please have a look :) \$\endgroup\$ – Junye Li May 23 '17 at 13:31
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There are several major issues I can see:

  1. You have a random and completely unnecessary #include "adder.v" statement. (Though I see you say you have removed it, but why then is it still in your question)

  2. Your adder module is not written properly. You have put an assign statement within an initial block which is not a legal syntax. Furthermore you don't want it to be done in an initial block as otherwise it would try to infer ROM type logic ("add these two numbers only at power up") using non-constant expressions which is not possible to do for synthesis. Get rid of theinitial statement.

    module adder(
        output reg [3:0] S_out,
        input      [3:0] S_in,
        input      [3:0] coin
    );
        assign S_out = S_in + coin;
    endmodule
    
  3. You cannot infer an instance of a module in an always block.

    always @(posedge CLK) begin 
        ...
        adder jjjjj(.S_out(S_out), .coin(coin), .S_in(S_in));//here is the error -> of course!!
        ...
    end 
    

    Remember you are not writing a program. Verilog is a HDL, you are describing hardware. Basically what you are describing here "always at the positive edge of CLK, suddenly add some extra hardware, then delete it again". That makes no sense as a construct and is an illegal syntax.

    Instead you should be inferring modules outside always blocks. All hardware must exist at synthesis, it cannot be dynamically created from nowhere.

  4. In fact that entire always block is complete nonsense. You are mixing blocking and non-blocking assignments, you are adding time delays which are not synthesisable (simulation only), you are trying to instantiate modules as in (3), you begin and end statements are all over the place, etc.

    I would highly recommend adopting the style of always using begin and end statements, and put each one on its own line - that will make it far easier for you and anyone else reading it to work out what you are trying to do. For example:

    always @ (posedge CLK) begin
        if (reset) begin
            //do reset stuff
        end else begin
            //do non-reset stuff
            //Notice how it is much clearer with stuff on separate lines. and well indented.
        end
    end
    
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