I'm trying to write one main module and one as secondary (called "adder"). However, I kept getting errors either telling me there are syntax errors with the "adder". Please help me with my code:
Here is the implementation of the module:
module adder(
output reg [3:0] S_out,
input [3:0] S_in,
input [3:0] coin
);
initial begin
assign S_out = S_in + coin;end
endmodule
and here is the main module:
module Assign2(
input Nickel,
input Dime,
input Quarter,
input Start,
output reg Release_Paper,
output reg Return_Coins
);
`include "adder.v"//this line is removed
wire CLK;
CLoK C1(CLK);
reg [3:0]S_in;
reg [3:0]S_out;
reg [3:0]coin;
wire [2:0]i;
assign i = {Quarter, Dime, Nickel};
wire reset;
parameter S0 = 4'b0000;
parameter S1 = 4'b0001;
parameter S2 = 4'b0010;
parameter S3 = 4'b0011;
parameter S4 = 4'b0100;
parameter S5 = 4'b0101;
parameter S6 = 4'b0110;
parameter S7 = 4'b0111;
parameter S8 = 4'b1000;
parameter S9 = 4'b1001;
assign reset = Start;
always @(posedge CLK) begin
if (reset == 1) begin
S_in = S0;
S_out = S0;
end
case(i)
3'b001: coin <= S1;
3'b010: coin <= S2;
3'b100: coin <= S5;
endcase
#100;
adder jjjjj(.S_out(S_out), .coin(coin), .S_in(S_in));//here is the error
if (S_out == 4'b1010) Release_Paper <= 1'b1;
else if (S_out > 4'b1010) Return_Coins <= 1'b1;
end
endmodule
EDIT: I have removed the include and here is the error message: [HDL 9-806] Syntax error near "addr". ["....Assign2HDL/Assign2.v":66]
The platform is Xilinx Vivado 2017.1, and I also tried on Xilinx ISE 13.4, which strangely has some issue with my clock:
Line 28: Non-constant loop condition not supported for forever
and here is the clock:
module CLoK(
output reg CLK
);
initial begin
CLK = 1'b0;
forever
#2 CLK = ~CLK;
end
endmodule