# Can I use 2 Flop synchronizer to migrate a pulse from one clock domain to another provided that clocks phase shifted but of same frequency?

I want to migrate this signal from CLKA to CLKB. Frequencies of both the clocks are same but they are out of phase.

Can 2-Flop synchronizer be used for this? Please note that the signal can be low/high for one CLKA clock cycle (pulse).

• CMD Input to a d type FF, clock to clkb. – Andy aka May 24 '17 at 13:17
• Is the phase known? Are the clocks coming from the same source (two different clock sources rated for the same frequency wont be exactly the same)? Does the pulse width of the CMD signal matter? – Tom Carpenter May 24 '17 at 13:18
• First off, is the phase relationship fixed or variable? As @TomCarpenter said, this really asks are they coming from the same source or from two different sources? That has a big bearing on the answer. – TonyM May 24 '17 at 14:50
• Hi @TomCarpenter Phase is variable. Source of both the clocks is same. – ashishdevre May 25 '17 at 5:29
• @TonyM Phase is variable. Source of both the clocks is same – ashishdevre May 25 '17 at 5:30

The issue is how much they're out of phase. If the data can change during the FF's setup and hold times you have a metastability problem and need to use 2 FFs: the second will be clocked when any ringing on the first is over. Otherwise 1 will suffice. PW limits are based on the same consideration.

• Clearly, the OP understands metastability. That isn't the question. And metastability is not "ringing". – Dave Tweed May 24 '17 at 13:58
• No, it's not clear that OP understands metastability. Metastability can look like ringing sometimes. – toiler Jun 21 '17 at 1:26

If the phase relationship is fixed, then a single FF should be sufficient. You always have two choices of which clock edge to use in order to make the timing work out.

If the phase relationship varies with time — and especially if it can vary by more than the clock period — then two FFs is not sufficient. There's still a small probably that a pulse will be missed. The technical term for this situation is "plesiochronous".

You'll need a more complex structure called an "elastic buffer" — essentially a shallow, 1-bit wide FIFO, which requires a minimum of three FFs for the data (determined by the maximum peak-to-peak excursion of the phase), plus some control logic.

I have a design for a 3-bit elastic store that I did a long time ago for a telecom application. It uses a total of 9 FFs, which is still simpler than a LUT-based 16x1 asynch FIFO and its control logic. If you want to see it, I'll try to dig it up.

• If the phase relationship is fixed and the routing is constrained, then 1 DFF can be used. Otherwise the routing delay can make the arrive just as the DFF is clocked. Routing (time delay) and phase (time delay) must guarantee DFF setup/hold time. – TonyM May 24 '17 at 13:31
• @TonyM: If the phase relationship is fixed, you always have two choices of which clock edge to use in order to make the timing work out. – Dave Tweed May 24 '17 at 13:36
• Something to fix in your answer, then. Timing constraints or 2 DFFs off on clock edge are clearer for others and simpler to work with (comb' between DFFs always has a CLK, not half) than 1 DFF and both clock edges. – TonyM May 24 '17 at 13:49
• Hi Dave, Thanks for the reply. I have used async FIFO to do this. Actually my system requires to pass 16-bit of DATA signal along with 1 bit of CMD signal (as shown in the diagram) from CLKA domain to CLKB domain. Since I had already used 16-bit wide async FIFO for DATA synchronization, I just added one bit in the data width of FIFO and used it for passing CMD signal. (Here, CMD and DATA are independent signals.). However, I am interested in the way you have done using 3-bit elastic store. Please share if you can find anything on it. – ashishdevre May 26 '17 at 9:47

Recommended reading: Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs from this web site.