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I was reading the LPDDR2 spec today out of curiosity. While browsing the spec I became curious about "how might one hypothetically design a minimal working LPDDR2 PHY on paper/for simulation, perhaps to release as an open source design?"

According to this answer, the internals of how LPDDR2 works are confidential. Additionally, according to this article, most SoC designers today use a (LP)DDR PHY IP. So schematics of memory chips and PHY internals are unlikely to be found online. However, I imagine there are people browsing EE.SE who would know about designing PHYs, and that some design techniques are not specific to (LP)DDR PHYs apply anyway.

Does there exist literature on how a memory PHY of might be designed at the schematic level (including simulation and DRC), or general techniques on how to design a (LP)DDR PHY?

If no to the above question, I'll reduce the scope to my immediate questions about LPDDR2, using the spec as a reference.

  • LPDDR2 specifics that all logic level I/O is relative to a V_ref (page 160), and that the memory controller generate voltages relative to V_ref to indicate high or low, even if V_ref is out of spec. What is the rationale (analog behavior) behind this design decision? How would a PHY generate these voltages (a simple summing amplifier?)?

  • LPDDR2 requires that supply voltages always obey certain requirements (page 26), such as voltage rails always being no more than 100mV within each other. What analog behavior within a LPDDR memory would require this behavior, even during the power-up phase, when voltages are likely to be erratic? Would circuitry inside the controller or memory chip be able to enforce these requirements?

  • Can the voltage-level generation/regulation circuitry as described in the above two bullet points be analyzed/created using pencil and paper approximations, or are the analog effects required to meet the conditions too precise to be reasonably analyzed on paper (thus, requiring a simulator)?

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  • \$\begingroup\$ referring an interface's threshold voltages to a separate voltage V_ref makes sense, if you think about it – that way, your memory and your e.g. CPU can run off separate supplies, as long as both sides agree on a common reference voltage. \$\endgroup\$ – Marcus Müller May 24 '17 at 22:18
  • \$\begingroup\$ I would expect in order for the designer to be successful in this low power transmission line compromise between low source <=50'impedance and high terminated impedance of 240 Ohms diff, that all the PWB stripline or microstrip tolerances for Zo, group delay and skin effect on ENIG surfaces are well characterized with TDR in fab shop tests to 5% tolerances rather than the usual 10% and material selection is critical. The slew rate and EQ training depends to much on these parameters with high Zo low capacitance loads of 2pF max. \$\endgroup\$ – Sunnyskyguy EE75 May 25 '17 at 1:10
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    \$\begingroup\$ Even using good substrate, I have seen good designers go thru a few iterations on Zo design from overestimating e and not doing Monte Carlo tolerance calculations, which I suggested to get it right 1st time. Polyamide was the substrate of choice back then. I've not seen this spec before but the 600mV +/-140mV margin is well defined for the fast rate. Getting there takes practice. \$\endgroup\$ – Sunnyskyguy EE75 May 25 '17 at 1:14
  • \$\begingroup\$ Current-mode latches are one approach. See the answer. \$\endgroup\$ – analogsystemsrf May 25 '17 at 2:31
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Here is a CML latch to think about

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ A few questions: 1. Does this circuit exist as part of the inputs of BOTH the PHY and memory device? 2. On the PHY side, logic family voltages will be converted to what the CML latch expects using a differential tx/rx I assume? 3. I don't see a negative rail for LPDDR. How is the negative rail generated on-die (buck/boost inductor is probably too large to fit on-die)? \$\endgroup\$ – cr1901 May 26 '17 at 12:17
  • \$\begingroup\$ Also, I didn't downvote, but can the downvoter specify what they'd want to see in this answer to make it better? \$\endgroup\$ – cr1901 May 26 '17 at 12:22

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