# Does using only NAND/NOR gates increase circuit delay?

I remember learning in school that one can construct any logical circuit from solely NAND or NOR gates.

First of all, I am wondering if this is how it's actually done: i.e. when Intel makes a CPU, do they build all the registers, etc. using NAND/NOR gates, or do they have some other fancier way of doing things?

Secondly, I'm wondering if constructing everything in this manner increases propagation delay compared to a circuit made using AND/OR/NOT gates as well.

I know that when using PMOS/NMOS configurations to build gates, an AND or an OR comes out as 2 stages as opposed to a NAND or a NOR which are both only 1. Since I know you can make an AND from 2 cascaded NANDs and an OR from 2 cascaded NORs, it seems as though propagation delay would not increase as long as manufacturers were using both NANDs and NORs.

Does anybody have any insight on all this, especially as to what is really done on manufactured ICs?

First of all, I am wondering if this is how it's actually done: i.e. when Intel makes a CPU, do they build all the registers, etc. using NAND/NOR gates, or do they have some other fancier way of doing things?

Registers aren't made out of gates, most often they are dedicated circuits. They can be seen as made with inverters (NOT), but only to a certain extent.

In CMOS technology, everlogic circuit is based on the inverter: NOR and NAND gates are just inverters with multiple inputs arranged in a clever way, basically. So the inverting gates are faster than non inverting ones, which are just inverting gates with a NOT at the output.

Also in dynamic logic, it's simpler to cascade two inverting blocks than putting NOT gates everywhere.

Consider that in some cases a circuit may be made out of separated blocks, so there may be a case in which the output is interfaced through one or more inverters for buffering.

And there is another advantage in that: integration. Having a small number of different gates helps in laying out the circuit, and uniforming the performance. Often libraries include logic blocks at different levels of complexity: transistor, gate, operator, or higher.

So, briefly, yes, fast processors are mostly using inverting gates.

• Okay, I think this makes sense to me. As a check - let's say I wanted to make a basic (e.g. 4-bit) adder using combinational logic (i.e. not by linking half-adders). Would I approach this problem trying to use only NAND and NOR gates, and as few of these as possible? Will this almost always yield a better design (in terms of delay/gate count) than if I approached the problem using a full repertoire of gates and then replaced AND/OR/NOT gates with their NAND/NOR equivalents? Apr 26, 2012 at 10:15
• @llakais in almost any case, yes. And at least it will be equal. But, for instance, I've designed an adder for a university course, and I've done two things: first, I've used 4:2 adder blocks with full-adders (blocks win!), and second, I've implemented the full-adder with pass transistor XOR gates, so sometimes there are different solutions. Apr 26, 2012 at 10:24
• I will mention that for adders, having a full-adder cell is usually the fastest, not a combination of gates.
– W5VO
Apr 26, 2012 at 12:11
• @W5VO well a full adder is basically a combination of an XOR and an AND gate...but indeed the XOR can be made in clever ways without using the basic gates Apr 26, 2012 at 13:13

My inclination with CMOS is to think of a basic building block as being an inverter preceded by an arbitrary combination of independent "and" and "or" gates with no interconnections between them; all of the following functions:

not (X and (Y or Z))
not (X or (Y and Z))
not (X and Y and Z)
not (X or Y or Z)


have essentially the same cost in silicon, even though only the latter two have names. Trying to compose the former two functions using some combination of NAND or NOR gates would yield something which was much bigger and slower than a direct realization would be.