# NMOS Inductor Circuit

I could not understand the logic of this circuit, connecting an inductor to the supply what will change? Considering that C1 acts like a short circuit in AC analysis why do we differentiate x and Vout ? Are not they the same node?! How would the circuit looks like when L1 becomes an open circuit? Why there is a connection between the middle of NMOS and the ground node, and how can we connect the outer middle part of NMOS anyway? Finally, I also did not understand the "limiting factor" part of the question

• The L+C form a resonator, damped by the RL load resistor which absorbs AC energy at the "right" frequency. The FET NMOS forms its channel between Source and Drain in the region named "bulk" which is shown as the middle of the symbol. – analogsystemsrf May 25 '17 at 17:30
• Thank you very much. Is there any advice about how to start analyzing? – utdlegend May 25 '17 at 17:35
• Model the FET as 10pF C_drain_bulk, transconductance of 10mA/volt, rout of 10,000 ohms. Use L of 100nH, C of 100pF, Rload of 50 Ohms. Fresonate will be approximately 50MHz. Z(C) is =j15 ohm, Z(L) (this is at resonance, thus equals Z(C), is also +j15 ohm. Apply 2 volts PP input, centered on the Vthreshold (for transient sim) – analogsystemsrf May 26 '17 at 2:34

I could not understand the logic of this circuit, connecting an inductor to the supply what will change?

The inductor acts as a way to bias the device. It is a short circuit at DC (so you can provide a DC bias current) but is an open-circuit at the frequency of interest. If you didn't have it there in this circuit your MOSFET would have no DC bias current and thus would be off. But yes, for AC analysis you simply remove the inductor.

Considering that C1 acts like a short circuit in AC analysis why do we differentiate x and Vout ? Are not they the same node?! How would the circuit looks like when L1 becomes an open circuit?

In AC analysis x = Vout only at infinite frequencies. We sometimes make the approximation that C1 acts like a short circuit but this is not rigorously true. Sometimes you may wish to study the effect of C1 on the frequency response. But you are correct, in this case the way the question is worded, it isn't important to distinguish them.

Why there is a connection between the middle of NMOS and the ground node, and how can we connect the outer middle part of NMOS anyway? Finally, I also did not understand the "limiting factor" part of the question

A MOSFET is a 4 terminal device. In discrete MOSFET's usually the 4th terminal, called the "bulk" or "substrate" is connected to the source terminal internally so you see the MOSFET as a 3 terminal device so the answer to how we connect the outer middle part is that we don't -- the manufacturers do it for us.

Alternatively if you are in an IC technology then you DO have control over this, but most processes are what are known as NWELL processes and will have the substrate grounded for an NMOS device no matter what.

• Thank you, do you have any explanation for this phrase : " Vin is large enough to drive X to high voltages". I am confused because it says that Vin changes sinusoidally so it can not always have LARGE enough values. Being an A class means that I am going the draw a complete (360 degree) output signal right? – utdlegend May 25 '17 at 18:55

The inductor supplies DC voltage to the circuit, but is an open circuit at the frequency of interest and so does not absorb any signal power. It also doubles the peak-to-peak output voltage swing, so if Vdd is 10V then X can go from 0V to 20V (with 10V being the midpoint).

How does it do this? In the idle condition (no signal input) X is 10V and the FET is drawing a quiescent current. When the input sine wave goes positive the FET draws more current. This increasing current also goes through L1, causing it to produce an opposing voltage which decreases the voltage at X. Voltage can continue to decline until it reaches zero, at which point the FET can't pull down any lower. Thus the output wave's negative half cycle can reach -10V.

When the input wave goes negative the FET draws less current, causing the inductor to produce an opposing voltage which adds to the supply voltage. Voltage at X then goes above Vdd, and can keep increasing until the FET is drawing no current. At this point X is double the supply voltage, and the output's positive peak is +10V.

(Note that this only applies when the amplifier is operating in class A, with the load absorbing energy that was stored in the inductor. If the load is removed or the FET is over-driven then the voltage at X could go much higher than 20V.)

Now that you know the peak-to-peak voltage across RL you can calculate the power in it. Since the amp is operating in class A (and assuming zero distortion) current in M1 swings from zero to twice the peak load current, and the average current drawn from the power supply is the same as the peak load current. Knowing this you can calculate the power drawn from the supply, and the efficiency of the circuit.