# Pwm frequency math challenge

I am trying to challenge myself to learn how to calculate cycles per second and integrate what I have learned through component behavior and data sheet test specs. Not an easy task with google as your only teacher. However, I have attempted to try to calculate the approx. Pwm hertz from my latest project in order to trouble shoot it. Please correct my math and understanding if I am wrong.

Pwm generator is 40106 inverter with estimated specs for 12v use:

High trigger=7V Low trigger=4.5v

Astable components 100k pot set to 50k .1uf cap

Math: Time constant : $rc =.0000001*50,000 =.005s$

Cap charge formula : $V_c=V_s(1-e^{-t/rc})=12(1-e^{(-.0023/.005)})=4.5V$

$V_c=7V$ with $t=.0045$ Difference of .0022 seconds from 4.5v to 7v This is the high output time on inverter

Cap discharge formula : $V_c=V_s(e^{-t/tc}) = 12(e^{-.0023/.005})=7.5V$

$V_c = 4.5V$ with $t=.0023$ Same difference of .0022s.

Total on/off cycle .0044 seconds $\frac{1}{.0044}=227Hz$

I realize discharge was to 7.5v not 7v just for consistent value sake. Go easy on me if I am way off. Just a hobbyist. Thanks for any help.

## 1 Answer

From the datasheet, 13. transfer Characteristics

                      Vdd  min typ - min(full temp)
Vh hysteresis voltage 5 V 0.5 0.8 - 0.5 - V
10 V 0.7 1.3 - 0.7 - V
15 V 0.9 1.8 - 0.9 - V


Thus I interpolate for 12V between 1.3V ~ 1.8V or ΔV=Vh = 1.5V typ

• The transition time, dT for a half cycle from Ic=C dV/dT or dT = C dV/Ic where the derivative slope dV=ΔV=Vh

• since Ic= Vdd/R and dV= 1.5V from above , you can now calculate f=1/(2dT) from all this math.
• just in case you are lost, the Cap current formula, Ic differentiates voltage dV/dT, while the circuit Voltage from R integrates current is linear over a small interval ΔV, is the same thing.
• and Ic = (Vdd/2 + ΔV/2) * 1/R
• or Ic=(Vcc+ΔV)/2R ( assuming waveform symmetry Vdd/2 almost...)
• thus dT = 2RC dV/(Vdd+ΔV) and dT * 2 = 1/f

• thus $f = \dfrac{{(Vdd+ΔV)}}{4RC \cdot ΔV}$ (corrected)

for R=50 [kΩ] , C=0.1 [uf] , Vdd=12 [V] , Vh=ΔV=1.5 [V] , f= ?[Hz]

if ΔV/(ΔV+Vdd) is 50% tolerance, then Δf will be ~ 50% tolerance.

For more precision use a comparator with <=1% parts.

simulate this circuit – Schematic created using CircuitLab

I corrected my misteaks;)

I now get 450 Hz but 396Hz on my Simulation. ... error on mean threshold..

• 1800hz I believe. Clearly I was very wrong :) I will review your formulas to get a better grasp. Thanks Tony. Commented May 25, 2017 at 19:08
• what tolerance do you have? did you measure ΔV, I think I did Ic wrong Commented May 25, 2017 at 19:13
• As for the hysteresis, I am getting multiple values depending on which data sheet. I still see about 2.5-3v approx between the 10-15v vdd test. Also, I have only begun to understand your instantaneous voltage change over time derivative calculus formula. Beyond me at this point how to use it properly. My understanding was to use the voltage over time formula to get how long the cap stays within the estimated 7v high and 4-4.5v low to trigger the high/low cycles. The inverter would dump/charge the cap between those thresholds. The "t" in the formula was the key to my thinking. I am a newbie Commented May 25, 2017 at 19:56
• try out my java link at end of answer..you may learn how to tweak the input of the fixed 5Vout logic thresholds and gm or RdsOn of any FET Commented May 25, 2017 at 20:07
• if you divide your answer 1800/4=450 you get the same as I (tada) Commented May 25, 2017 at 20:10