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Hi, in the image below (taken from Design of CMOS Analog Design Circuits by Razavi), a high gain amplifier is used to provide common mode sense and feeback by controlling the current through M3 and M4. The idea is that if both Vout1 and Vout2 rise, then Ve rises, and the current through M3 and M4 rises, which then brings down the output common mode level.

Now I just want to know if my understanding of why exactly this brings the common mode level down is correct. Please correct me if my explanation below is wrong.

Raising Ve will raise the current through M3 and M4, but the transistors stacked on top are biased for a different current (their gate voltages are set). To satisfy KCL at Vout1 and Vout2, the drain voltages move down so that the same currents flow through the cascode PMOS and NMOS transistors and M3 and M4.

In other words, the voltages rise or fall to favor equal currents throughout the branch except for the top PMOS transistors, above the folding node.

I hope my explanation makes sense. Do correct me if I am wrong.

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    \$\begingroup\$ but the transistors stacked on top You should be more specific which transistors you mean. The circuit works as follows: the Top PMOS (with sources on VDD) are current mirror outputs and they bias the whole stack of transistors (down to GND) at a certain bias current. M3 and M4 are also current sources. If the current sourced by M3, M4 is lower the current from the top PMOS, Vout1,2 will rise. When this happens Vout,cm rises as well. This increases VE and thus also the current provided by M3,4 until Id, M3,4 matches the current from the top (minus Iss/2). \$\endgroup\$ May 26, 2017 at 19:36
  • \$\begingroup\$ I meant the cascode NMOS and PMOS transistors, by "transistors stacked on top". I assumed Vout1,2 would rise in order to equalize the currents through these transistors (excluding the PMOS whose sources are tied to VDD). I guess my actual question is, what actual mechanism causes Vout1, Vout2 to rise when the currents through M3, M4 lower. \$\endgroup\$
    – user124713
    May 26, 2017 at 19:43
  • \$\begingroup\$ Is it because when the currents through M3 and M4 are lower than the Id(top PMOS)-Iss/2, the top PMOS transistors enter triode region? My question basically is this: What controls the drain voltage of the cascode transistors? \$\endgroup\$
    – user124713
    May 26, 2017 at 19:54
  • \$\begingroup\$ To explain the CMM-feedback I would use the same circuit without the cascodes and without M1, M2. Then the drain voltages are controlled by the currents from above and below. Ideally when those currents are equal, the drain voltages are at VDD/2. The feedback loop sets the drain voltages to Vref (which could be VDD/2). Then add diffpair M1, M2. Since these are current out you need a low impedance point to take the currents. This is made by the top PMOS cascodes. For symmetry also NMOS cascodes are added. \$\endgroup\$ May 26, 2017 at 20:50
  • \$\begingroup\$ Indeed if the CMM voltage was not controlled the transistors could enter triode region which must be avoided as that lowers the MOSFET's output impedance. The CMM feedback makes sure that the transistors operate in saturation region. \$\endgroup\$ May 26, 2017 at 20:53

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It's a lot easier to think of this stuff in the small-signal sense.

Look at the circuit from the point of view of M3 and M4 to Vout1 and Vout2 respectively.

It is just a cascode circuit. So you know that the vout/vin transfer function from the input (gate of M3) to the output (Vout1) is inverting. So a positive going voltage at the gates of M3 and M4 will cause a negative going excursion at the drains of their respective "cascode" transistors.

So I'll walk you through the loop.

Suppose Vout1 and Vout2 each go up by exactly the same amount delV. Since the delV on either side of R1 and R2 is the same, that means no signal current flows and hence no signal voltage develops across R1 and R2, therefore the midpoint sees exactly delV.

This goes to the op-amp + input which makes Ve rise up a little bit.

We know that Vout1/Ve is "like a cascoded CS amp" which we know has an inverting gain. So Ve goes up and thus Vout1 and Vout2 go down a little bit. Hence the feedback is negative.

Now, if you want to think of it in the large-signal sense that is fine too. (That is essentially what you're trying to do). But in this case your understanding is incorrect. The NMOS devices do indeed have a fixed gate voltage, but its Vgs is NOT fixed. As an example, suppose that all you had in the circuit for the time being was M3 and the NMOS stacked on top of it. Now suppose you came along and said "I'm going to increase the current through M3". What does the NMOS transistor stacked on top do? Its gate is fixed, but it now wants a bigger Vgs to accomodate this larger current so its source (M3's drain) will actually go down a little bit. That's all. And the current you set in M3 will get passed.

What's actually going on in your situation in a large signal sense is this. M4 is a current source which battles the PMOS DEVICES at the top of the leg.

When M4 says "Give me a bigger current", the only thing the PMOS transistors can do is to swing their drain voltages LOWER to increase their VSD to try to accomodate the current increase.

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  • \$\begingroup\$ Thank you for such a detailed explanation! Your last point was actually what I was trying to make, and I believe I did not word my description precisely. There is a current increase through M3 and M4, and that has to match the currenth through the PMOS transistors too. So in response, they increase the drain-source voltages, so as to equalize the currents through them and the NMOS. Yes, it is easy to view it from a small-signal perspective, but I was not satisfied doing it because after all this phenomenon goes on in a large-signal sense. But thank you still! \$\endgroup\$
    – user124713
    May 26, 2017 at 19:58
  • \$\begingroup\$ For a quiet Vcm, you might use FETs with short channels so the Rout is low and the Vcm loop has low gain, for stability. \$\endgroup\$ May 27, 2017 at 3:45

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