STD_LOGIC_VECTOR to INTEGER VHDL

The problem is to find a modulo when a three digit number is divided by its last two digits. But the three digit number is received in a binary form. So I first want to change the binary form into integer form then use the mod operator.

• Maybe your signal definitions for divident_int (and others) should be defined as unsigned? If you convert a negative int (that starts with a MSB=1), it may be truncated to a value of 0? – Nazar May 27 '17 at 13:48
• Your process is only called once (no sensitivity list) and the value of "dividend_int" is only updated after reaching the WAIT statement. modcalc looks like a combinatorial entity (no clock). You don't need any process. Alternatively, you could use a variable for dividend_int, modulo_int and modulo_1 – TEMLIB May 27 '17 at 14:15

Why do you paste your code as an image?! This makes it harder for us to help you. Please don't do that next time.

The answer is given by TEMLIB. You have two options:

1) Make a triggered process, with the internal value as variables.

begin
process(divident)
variable divident_int : integer;
variable modulo_1_int : integer;
variable modulo_int : integer;
begin
divident_int := to_integer(unsigned(divident));
modulo_1_int := divident_int mod divis_1;
modulo_int := divident_int mod modulo_1_int;
modulo <= std_logic_vector(to_unsigned(modulo_int, modulo'length));
end process;
end architecture;


2) leave out the process (and keep the signals)

begin
divident_int <= to_integer(unsigned(divident));
modulo_1 <= divident_int mod divis_1;
modulo_int <= divident_int mod modulo_1;
modulo <= std_logic_vector(to_unsigned(modulo_int, modulo'length));
end architecture;

• Thank you so much for your help! I accept your suggestion as well. I won't do so again. – Hintsa Fisseha May 30 '17 at 8:25