I was asked to determine the maximum value of the load $R_L$ so that the circuit works properly, under the assumption that $r_o$ is infinite. Is that a standard DC calculation, hence do I simply write out the condition for all the transistors to be in saturation and deduce from that the maximum value of the load, or is it something more intricate that requires small signal evaluation?

• Would anyone here kindly share their thoughts? I am simply vacillating whether this is a simple DC question based on the requirement that the transistors are all in saturation or whether rather a small signal analysis is required – peripatein May 27 '17 at 21:20
• Yes, determine the minimum compliance voltage of your current source, then ohms law for Rl – sstobbe May 27 '17 at 22:46
• @sstobbe what do you mean by minimum compliance voltage? Don't I merely need to make sure Vgs>vth and Vdg>-vth (hence assuring saturation)? – peripatein May 27 '17 at 22:59
• Well, that criteria ensures saturation, you also want to ensure the correct Vov for your desired output current. – sstobbe May 28 '17 at 0:05

From the specifications provided in the question you know that Q6 & Q5 have a drain current of 1 mA. You have previously shown that this circuit does behave as a 1 to 1 current mirror. Thus, Q{1,2,3,4} also all operate at a drain current of 1 mA. Since they all have the same geometery they all operate at the same overdrive voltage.

The current of an NMOS in saturation is,

$$Id = \dfrac{k_n'}{2}\dfrac{W}{L} \left( V_{gs} - V_t \right)^2$$

The overdrive voltage is,

$$V_{ov} = V_{gs} - V_t$$

Rearrange and solve for the $V_{ov}$,

$$V_{ov} = \sqrt{\dfrac{2(1\textrm{mA})}{8 \textrm{mA/V^2}}} = 500 \textrm{mV}$$

Saturation of an NMOS is achieved when the gate-drain voltage is less than the threshold voltage $V_t$, i.e. $V_{gd} < V_t$. This is also equivalent to stating,

$$V_{gd} = V_{gs}-V_{ds}$$

$$V_{ds} > V_{gs} - V_t$$

$$V_{ds} > V_{ov}$$

For your question, Q3 & Q2 both require at a minimum 1 $V_{ov}$ for $V_{ds}$. Q1 requires the same $V_{ov}$ as Q4 for 1 mA operation, which is Vgs = 1 V. So the minimum output compliance is the sum of the each minimum $V_{ds}$ as,

$$V_{o,min} = 0.5 + 0.5 + 1 = 2 \textrm{V}$$

The maximum permissible load resistance tied to Vdd is one which drops the output to its minimum compliance.

$$R_{L,max} = \dfrac{5-2}{0.001} = 3 \textrm{k}\Omega$$

• Shouldn't the minimum Vds of Q1 be Vgs-Vt=1-0.5=0.5V, yielding 5-1.5/(0.001)=3.5K? – peripatein May 28 '17 at 10:02
• For the bottom NMOS Q1, Vds = Vgs, so it must be at the Vgs for Id = kp/2W/L(Vov)^2 for 1 mA opperation – sstobbe May 28 '17 at 10:07