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I recently got Webpack to sorta work for me on my Linux system... but I tried using ISim for simulation of my designs and got hit by a problem. And from what I can tell, this problem isn't Xilinx's problem, since I'm not using a supported OS(Arch Linux)... and I can't figure out how to fix it... so I'm going to do something that hopefully is easier in the long run.

Anyway, I want to use ghdl/gtkwave for simulation, and then use Webpack's tools only for when I need to generate a bitstream for uploading to my FPGA... And I want it all to be run easily from a makefile. Of all the makefiles I've seen for using their command line tools though, they all require a project file. I'd really rather just specify files manually somehow in my makefile. I'd rather not have to, every time I add a file, change the project and my makefile. Is this possible?

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Not that I am aware. Another approach is to use a script instead of a makefile. The script can then create the project file so you do not to manually edit multiple files.

You can use TCL to drive the ISE tools. The ISE tools will generate example code for you. More information on using TCL can be found here, http://devbisme.webfactional.com/blogs/devbisme/2012/04/03/running-weeds

If you want a Python option for building Xilinx ISE projects, see Guenter Dannoritzer's Python scripts, which generate the underling tcl, but the OO interface in Python is better than generating tcl directly, http://www.myhdl.org/doku.php/projects:ise_py. I have made some updates to the scripts here, https://bitbucket.org/cfelton/examples/src/tip/tools

An example, you can quickly and as easily create an ISE project.

# set up pin configuration for the FPGA
fpga = Fpga(path=ppath)
fpga.setPin('clk', 'P124')
fpga.setPin('srst', 'P8')
fpga.setPin('led<0>', 'P92')
fpga.setPin('led<1>', 'P93')
fpga.setPin('led<2>', 'P95')
fpga.setPin('led<3>', 'P96')
fpga.setPin('led<4>', 'P97')
fpga.setPin('led<5>', 'P98')
fpga.setPin('led<6>', 'P99')
fpga.setPin('led<7>', 'P100')
fpga.setDevice('spartan3', 'xc3s400', 'tq144', '-5')

imp = Xilinx(ppath, 'stroby')

imp.setFpga(fpga)
imp.addHdl((vfile))
imp.createTcl() 
imp.run()
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Is this any use:

http://www.excamera.com/sphinx/fpga-makefile.html

Googling "xilinx makefile" shows quite a lot of people doing similar things.

My personal approach: For non-EDK systems, I have a script-based system which just runs through all the steps required in order without any "cleverness" - usually these designs small, so a complete run only takes 5 mins or so

Larger designs are usually done within EDK, then I build on top of Xilinx's makefile (including theirs into mine)

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