# A question about a current sensing circuit

While i was searching about accurate circuits to sense currents in high side, i found a very interesting circuit proposed by linear technoloy, but i didn't understand the role of the NMOS at the output.

What i understood is that the current that flows on the Nmos and the output resistor is : Vshunt/Rin tthen the output voltage is : Vshunt*Rout/Rin.

The problem is that i thought that the op amp wasn't operating in the linear zone, but when i simulate it i found that the it is operating in the linear zone.

The second problem is that the voltage on the NMOS (VDS) is the same as the common mode and i thought that it would be 0V ( since the current flows into it ) So my question is how this circuit functions generaly ? Thank you for your help.

• So, what is your question? May 29, 2017 at 14:01
• Dave provides a great answer, just remember that everything except the final 2k resistor forms a precision current mirror. It is current output not voltage May 29, 2017 at 14:45

The general idea is that the opamp drives the NMOS until the voltage drop across the upper 200Ω resistor is the same as the voltage drop across the 0.1Ω sense resistor. The current required to do this (1/2000 of the load current) also flows through the 2kΩ resistor, which is what gives you a ground-referenced output voltage that is 1V per load amp.

A MOSFET is preferred here because there is no DC gate current that would affect the accuracy. However, note that this requires the opamp to be able to drive the gate to a voltage equal to the highest expected output voltage PLUS the threshold Vgs of the transistor.

Since the total voltage across the two resistors is strictly proportional to the load current because of the action of the opamp, all of the remaining source voltage must be dropped across the transistor.

Note that there is essentially zero current through — and zero voltage drop across — the lower 200Ω resistor. It is there to cancel out any offset created by the opamp's input bias current.

It's very curious that the only resistor for which a tolerance is specified is the gate resistor. This is actually the resistor with the lowest requirement for tight tolerance — the tolerances for all of the other resistors is actually much more important!

• I totally agree with what you said, thank you. Doest the op amp operate as a comparator or linear ? Because when i simulate on LTSPICE, i find that the output of the op amp variates when the current variates. Same thing with VDSon, I expect a low VDS ( VDSon ) but I find a VDS equal to VBAT minus the voltage of Rout. The NMOS conduct the current but VDS is not equal to VDSon. I'm trying to figure out why but i dont know why ... May 29, 2017 at 14:50
• Both the opamp and the transistor are operating linearly. Negative feedback (keep in mind that the transistor inverts the feedback signal) keeps the two opamp inputs at the same voltage. Trust the simulation; it sounds like it is working exactly right. But I'm not sure what you mean by "VDSon" -- there is no fixed value of Vds for a MOSFET. May 29, 2017 at 14:56
• You are right, there is a curve in the datasheet ot the mosfet that represents Id as a function of Vds. I didn't get how the transistor inverts the feedbackof the op amp ? And then, what is the equation at the output of the amplifier ? Thank you very much for your time. May 29, 2017 at 15:46
• When the opamp output rises, the current through the transistor increases, which increases the voltage drop across the upper 200-ohm resistor. This causes the signal at the "+" input of the opamp to fall -- negative feedback. I'm not sure what kind of equation you're looking for. The voltage at the opamp output will be $V_{gate} = V_{out} + V_{gs(th)}$, and $V_{out} = I_{load}\cdot 1\Omega$. Note that since the transistor is in the feedback loop, the opamp automatically corrects for any irregularities in its characteristics, such as manufacturing variations in the exact value of Vgs. May 29, 2017 at 16:28
• I will try to Order chronologically what happens: First, no curret flows in the load, the transistor is not driven then open then no current flows on Rout. When a current flows in the load, V+>V- for a little time then the op amp output is saturated (5V), then the nmos is driven and i=Iload/2000 flows into the mosfet and the Rout. Then V+ = V- ( negative feedback ) and then the output of the op amp is defined bu Vout+ Vgsth ( no equation as a function of the inputs of the op amp ) May 30, 2017 at 11:26