2
\$\begingroup\$

I'm often confused what the meaning of 'speed' is in analog circuits. To me it seems that the higher the cutoff frequency, the 'faster' the circuit is. In other words, a higher frequency input signal can be processed.

The reason I'm confused is that I just read about the 'speed' of an analog circuit being affected by the current. To my knowledge, the current doesn't affect the time constant (R or C) and as a result doesn't affect the bandwidth, so how can for e.g. greater current result in a 'faster' circuit? Is it something to do with the rate of change of capacitance voltage increasing i.e. \$I_c = C\frac{dV_c}{dt}\$ ? Is this related to the slew rate?

Could it be that a higher current increases the transconductance and therefore the unity-gain bandwidth?

In the digital world, the meaning of speed is very straight-forward but there seem to be too many different meanings of speed in the analog world.

\$\endgroup\$
  • \$\begingroup\$ You're on the right path - in many circuits, unavoidable capacitance sets an upper frequency limit, either because of RC product, or because of dV/dt. \$\endgroup\$ – glen_geek May 29 '17 at 14:24
6
\$\begingroup\$

Take an example of a simple common-emitter BJT amplifier: -

enter image description here

For low frequencies, the voltage gain is fairly well approximated by RL/RE but, as frequency increases, the internal miller capacitance across the base-collector region starts to impose negative feedback and reduces gain.

If RL and RE are made ten times smaller (as a result of operating at an emitter current that is ten times greater), the frequency that which the miller capacitor starts to impose unwanted effects gets pushed up to a higher frequency.

It works the same with hanging an external load on the output - this usually means a little bit extra capacitance gets put in parallel with RL and this means the -3 dB operating frequency gets lowered. If RL and RE are much smaller (increased IE) then this can be somewhat alleviated.

So, here's an example where operating at a higher current gives a wider bandwidth.

Using a totally different example of a common collector colpitts oscillator: -

enter image description here

Fundamental to the working of this oscillator is the "hidden" resistance inside the emitter of the BJT (rE) - it is necessary to be there or the circuit won't oscillate (Barkhausen criteria not met). BUT, if the losses in the inductor are too high (such as in UHF oscillators) and rE is too large in value, the circuit won't oscillate. So, in order to reduce rE, collector current is increased by biasing the base a bit harder.

Because rE = 26 mV/Ie, a bigger collector/emitter current means a lower rE.

\$\endgroup\$
4
\$\begingroup\$

There are two kinds of speeds:

  • Linear/small signal speed

On a finished product, this is bandwidth. On a component like an opamp where you set the gain, this is gain-bandwidth product.

Using higher idle current allows to use lower value resistors, it also gives transistors higher transconductance. If parasitic capacitors stay the same, reducing R shifts RC poles to higher frequency and thus increases bandwidth.

Note the increase in bandwidth does not come from the increase in current, but from you (the designer) being able to use lower impedances due to the higher current.

There is another effect also. Transistor speed depends on current, via their transconductance (gm). Take a MOSFET for example. At lower current, the FET has lower gm. So you have to move its Vgs a lot more to go from 1mA to 2mA, than to go from 11mA to 12mA. Now, the gate is a capacitor. Thus, if it is driven from a highish impedance, the low-current, low-gm FET will be slower.

  • Non-linear speed

When one of the transistors turns off or saturates, the circuit is no longer operating in small-signal, linear mode. For example, an opamp slewing usually has one of the input pair transistors turned off.

In these situations, speed is usually determined by the amount of current available to charge a capacitor, or to push or pull charge into a semiconductor junction. For example:

  • Slew rate (V/µs) depends on input stage current charging the compensation capacitor.
  • Coming out of clipping involves turning a few transistors back on (ie, base currents have to charge b-e junctions from 0V to 0.6V) or worse, pulling transistors out of saturation (ie, base current has to pull charge out of b-e junction).

Having more available current, which usually comes down to having higher idle current in the input stage of an opamp, speeds up these things.

Some topologies (like current feedback) can deliver more current on-demand and sidestep these problems, but of course they can introduce others (like worse nonlinearity, or in the case of current feedback, low impedance negative input).

...and now something different, yet very similar: This is the load transient response of a micropower LDO. Note a LDO is an error amplifier driving a pass transistor. The error amp has a limited slew rate, limited output current, and the pass transistor has capacitance...

Look at the graph when the 100mA load current is quickly removed. Notice the output voltage jumps up by 200mV.

enter image description here

This is because this micropower LDO has very low current available to drive the pass transistor gate. So when the load current is removed, it takes a while to discharge the gate of the pass transistor to lower the current going through. As a result, the output cap ends up overcharged by 200mV.

The following events are even more interesting. Between 2 and 3 ms on the graph, the 100µA load current discharges the output capacitor. Output voltage is above its set point, so the pass transistor is completely shut off. The LDO's error amp is clipped, just like an opamp.

And when the output voltage falls below its set point, notice that it keeps falling (at t=3ms). It takes a while for the internal error amp to come out of clipping, reset the charge accumulated in its various internal capacitors, and resume normal operations.

By that time, output voltage has fallen by a lot... so the internal error amp panics, slews, and clips in the other direction which results in maximum current going through the pass device, as shown by the sharp rise in output voltage.

It overshoots its target, and... clips again, and slews back in the other direction... a few times, until it finally settles.

This is related to your question, because the various non-linear/clipping/slewing effects exhibited here are all related to how much current the internal stages have available to charge/discharge capacitors and junctions.

--- EDIT

Consider the following, which is just a FET biased as a common source amplifier. The current source and 1F cap is a way to set the bias current at DC, while shorting the source to ground at AC in the simulator, to avoid having to manually set a Vgs.

schematic

simulate this circuit – Schematic created using CircuitLab

The FET's drain is connected to the supply directly, so we don't have any Miller effect. This emulates a cascode configuration.

Question: what is the transfer function of Drain Current Id versus V(V1) depending on the bias current I1?

gm is the transconductance:

\$ g_m = dI_{R2}/dV_{gs} \$

In small-signal AC analysis, this is simplified as:

\$ I_{R2} = g_m V_{gs} \$

However, gm is proportional to current. So, the overall transfer function of this FET will be proportional to drain current.

Our FET is driven through a 10k resistor, and its grid is a capacitor Cgs, so we will have a pole (R1 * Cgs is a lowpass). Since Cgs is relatively constant, this pole does not depend on bias current.

Let's step I1 from 1mA to 1A, and plot Id (or I in R2) with frequency:

enter image description here

We get nicely spaced curves on our log-graph, which means, just as predicted, that our gain is proportional to bias current. But the pole is always at the same frequency.

Now, you gonna ask, "but how can the green curve with high bias be faster than the blue one with low bias since they have the exact same bandwidth??????"

Simple. Higher bias case gives same bandwidth, but higher gain, therefore it gives higher gain-bandwidth product (GBW). This means it is faster. If your device has a fixed GBW, using feedback, you can throw away some gain and convert it into more bandwidth.

Check this info on GBW.

\$\endgroup\$
  • \$\begingroup\$ Thanks. Can you please explain this part: "Transistor speed depends on current, via their transconductance (gm)...." I didn't understand the part where you mention that the current increase by increasing Vgs will be slow due to lower gm; I thought you already set a low current. As for the gate capacitance, you're saying that since the current is low, the capacitance will take longer to charge and will therefore be slow right? \$\endgroup\$ – eenn May 29 '17 at 15:57
  • \$\begingroup\$ I edited my answer. \$\endgroup\$ – peufeu May 29 '17 at 18:49
1
\$\begingroup\$

For many circuits, you can find gm/C setting the time constant. Setting the speed.

In MOSFETS, gm is set by process, by Width/gateLength, # stripes, and gate voltage (aka channel current).

In bipolars, gm is Ie/0.026; at 26mA, gm is 1 and power gains are enormous.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.